# 2D CFET contact-to-parasitic-to-PPA evidence ladder model card

- Version: 2026-08-25-v101
- Experiment: SA-DEV-2D-CFET-PPA-003
- Execution: precomputed browser CSV replay only
- Rows: 6144

## Purpose

Show why a channel or architecture claim cannot skip contact resistance, local-interconnect resistance and capacitance, extraction maturity, compact-model scope, circuit context, and replacement evidence when it becomes a PPA statement.

## Model

The generator uses only original SemiAgora assumed resistance, capacitance, load, voltage, footprint, and maturity states. First-order RC equations produce rise/fall delay, an equivalent 15-stage ring-frequency proxy, capacitive transition energy, a normalized routing-adjusted footprint, and a within-packet delay-energy-area product.

Zero-contact and intrinsic-only rows are intentionally incomplete references. They remain in the packet to reveal how much optimism appears when contact or layout RC is omitted. Contradiction flags prevent those references from becoming a performance recommendation.

## Evidence ladder

The model separates four extraction states and three compact-model states. Every row identifies the next owned evidence needed: geometry, contact metrology, I-V/C-V, model provenance, extraction settings and convergence, layout/circuit correlation, variation, thermal context, and accountable review.

## Non-claims

This is not a quantum-transport, TCAD, compact-model, PEX, SPICE, STA, power, thermal, Monte Carlo, A2, foundry, architecture-ranking, or signoff result. It does not reproduce any source value, dimension, process flow, figure, table, equation, model, or reported PPA conclusion.

## Rights

The source spine keeps official and primary links, metadata, and original synthesis only. Follow each rights holder's current terms before using the linked publication or resource.