{
  "schema": "semiagora.2d-cfet-contact-parasitic-ppa-source-spine.v1",
  "version": "2026-08-25-v101",
  "experimentId": "SA-DEV-2D-CFET-PPA-003",
  "generatedDate": "2026-08-25",
  "rightsPolicy": "Use official or primary links, bibliographic metadata, abstract-level scope, and original synthesis only. No publication body, figure, table, equation, process flow, dimension, model parameter, device value, PPA result, code, or dataset is mirrored.",
  "sources": [
    {
      "id": "src-arxiv-2d-cfet-a2-2607-12707",
      "label": "2D GAA CFET multiscale PPA preprint metadata",
      "organization": "arXiv / research authors",
      "url": "https://arxiv.org/abs/2607.12707",
      "sourceClass": "primary-preprint-metadata",
      "rights": "Public metadata, abstract, and link only; no PDF text, figure, table, equation, process dimension, model parameter, or PPA result is mirrored.",
      "note": "Scope anchor for the contact-to-parasitic-to-circuit evidence chain; all packet numbers remain original SemiAgora assumptions."
    },
    {
      "id": "src-imec-2d-material-logic-roadmap",
      "label": "imec: 2D-material devices in the logic scaling roadmap",
      "organization": "imec",
      "url": "https://www.imec-int.com/en/articles/introducing-2d-material-based-devices-logic-scaling-roadmap",
      "sourceClass": "rights-holder-research-roadmap",
      "rights": "Rights-holder link and original synthesis only; no article text, image, figure, process flow, device value, or material recommendation is copied.",
      "note": "Integration, contact, doping, variability, and staged-evidence vocabulary anchor."
    },
    {
      "id": "src-imec-monolithic-cfet-contacts-2024",
      "label": "imec: monolithic CFET stacked bottom and top contacts",
      "organization": "imec",
      "url": "https://www.imec-int.com/en/press/imec-demonstrates-functional-monolithic-cfet-devices-stacked-bottom-and-top-contacts",
      "sourceClass": "rights-holder-research-summary",
      "rights": "Rights-holder link and original synthesis only; no image, process condition, device curve, yield value, or reported result is reused.",
      "note": "Stacked-contact, frontside/backside access, isolation, and process-window evidence vocabulary anchor."
    },
    {
      "id": "src-imec-mcfet-scaling-2026",
      "label": "imec: scaling monolithic CFET across logic nodes",
      "organization": "imec",
      "url": "https://www.imec-int.com/en/articles/performance-boosters-scale-monolithic-cfet-across-multiple-logic-technology-nodes",
      "sourceClass": "rights-holder-research-summary",
      "rights": "Rights-holder link and original synthesis only; no ring-oscillator result, layout dimension, device curve, figure, or process detail is copied.",
      "note": "Device-to-ring-oscillator PPA handoff and backside-contact scope anchor without importing reported values."
    },
    {
      "id": "src-imec-logic-roadmap",
      "label": "imec: logic technology roadmap",
      "organization": "imec",
      "url": "https://www.imec-int.com/en/articles/view-logic-technology-roadmap",
      "sourceClass": "rights-holder-research-roadmap",
      "rights": "Rights-holder link and original synthesis only; no figures, dimensions, materials table, or performance result is copied.",
      "note": "FEOL/MOL/BEOL, contact resistance, local interconnect, via, routing, and DTCO vocabulary anchor."
    },
    {
      "id": "src-nist-irds-metrology-2024",
      "label": "NIST: IRDS 2024 metrology chapter",
      "organization": "NIST / IRDS",
      "url": "https://www.nist.gov/publications/international-roadmap-devices-and-systems-tm-2024-metrology",
      "sourceClass": "government-roadmap-metadata",
      "rights": "Official publication metadata and link only; no roadmap body, table, figure, or requirement is mirrored.",
      "note": "Measurement readiness, structure-function linkage, uncertainty, and manufacturability evidence anchor."
    },
    {
      "id": "src-nist-emerging-fet-benchmarking",
      "label": "NIST: reporting and benchmarking emerging FETs",
      "organization": "NIST / Nature Electronics authors",
      "url": "https://www.nist.gov/publications/how-report-and-benchmark-emerging-field-effect-transistors",
      "sourceClass": "government-primary-publication-metadata",
      "rights": "Official publication metadata and link only; no paper body, guideline text, figure, table, benchmark, or device value is copied.",
      "note": "Geometry, contact, bias, extraction, and comparison-contract evidence anchor."
    },
    {
      "id": "src-nist-2d-interface-flatness",
      "label": "NIST: 2D interface flatness and contact-region metrology",
      "organization": "NIST",
      "url": "https://www.nist.gov/news-events/news/2022/06/road-tiny-transistors-how-flat-flat",
      "sourceClass": "government-research-summary",
      "rights": "Official link and original synthesis only; no image, microscopy result, dimension, device value, or article text is copied.",
      "note": "Interface morphology, contact-region structure, and measurement boundary anchor."
    },
    {
      "id": "src-bsim-models",
      "label": "UC Berkeley BSIM model families",
      "organization": "UC Berkeley BSIM Group",
      "url": "https://www.bsim.berkeley.edu/models/",
      "sourceClass": "compact-model-reference",
      "rights": "Official model distribution and documentation links; model-specific licenses apply. No package, parameter, equation, or code is mirrored.",
      "note": "Compact-model provenance and replacement-model boundary anchor."
    }
  ],
  "claimMap": [
    {
      "nodeId": "kn-fi-061",
      "topic": "Contact formation and specific resistance",
      "evidence": [
        "src-imec-2d-material-logic-roadmap",
        "src-imec-monolithic-cfet-contacts-2024",
        "src-nist-2d-interface-flatness"
      ],
      "packetOutputs": [
        "four explicit contact hypotheses",
        "contact omission contradiction flag",
        "owned contact-metrology replacement slot"
      ]
    },
    {
      "nodeId": "kn-dv-080",
      "topic": "Compact models and extraction",
      "evidence": [
        "src-bsim-models",
        "src-nist-emerging-fet-benchmarking",
        "src-arxiv-2d-cfet-a2-2607-12707"
      ],
      "packetOutputs": [
        "three model-maturity states",
        "four extraction-maturity states",
        "model-scope contradiction gates"
      ]
    },
    {
      "nodeId": "kn-dv-084",
      "topic": "CFET stacking and integration",
      "evidence": [
        "src-imec-logic-roadmap",
        "src-imec-monolithic-cfet-contacts-2024",
        "src-imec-mcfet-scaling-2026",
        "src-imec-2d-material-logic-roadmap"
      ],
      "packetOutputs": [
        "2D CFET assumption card",
        "stack/contact/parasitic integration evidence ladder",
        "no architecture winner boundary"
      ]
    },
    {
      "nodeId": "kn-dvf-172",
      "topic": "RC parasitic extraction",
      "evidence": [
        "src-imec-logic-roadmap",
        "src-nist-irds-metrology-2024",
        "src-arxiv-2d-cfet-a2-2607-12707"
      ],
      "packetOutputs": [
        "schematic-to-corner extraction ladder",
        "RC-to-delay/energy/area handoff",
        "owned geometry and extraction replacement gate"
      ]
    }
  ],
  "reviewBoundary": [
    "The preprint is a scope signal, not accepted truth; no external result enters the generated rows.",
    "A rights-holder research summary is not a foundry rule, process recipe, calibrated model, or product recommendation.",
    "The packet exposes equation and evidence dependencies but cannot establish A2 feasibility, CFET superiority, or PPA readiness."
  ]
}