# SKY130_SRAM_WRITE_BOUNDARY_001 model notes

- Cell: the same SemiAgora 6T SKY130 schematic and sizes used by SKY130_SRAM_READ_001.
- PDK: SKY130A, TT compact models, 27 C, ngspice 42.
- Metric: a named dynamic write-success boundary, not a generic write-margin number.
- Stimulus axes: wordline amplitude (0.8 to 1.8 V) and ideal cell-VDD during a 3 ns write pulse (1.8 to 1.2 V).
- Initial state: Q=0, QB=1; intended state: Q=1, QB=0.
- Success criterion: after VDD restoration at 7.5 ns, Q > 1.35 V and QB < 0.45 V.
- The write delay is the first Q/QB crossing after the pulse begins, referenced to the 2.1 ns stimulus midpoint.
- Important exclusions: WSNM, BLVM, WLVM, N-curve, mismatch, PVT, half-select, assist driver impedance, extracted parasitics, and measured silicon.
- Concept anchor: A. Grossar et al., IEEE JSSC 41(11), 2006, DOI 10.1109/JSSC.2006.883344. The results and figures here are original SemiAgora executions.