# SA-DEV-CFET-001 - CFET contact/interconnect parasitic map

## Purpose

Teach why CFET density and drive claims must travel with contact resistance, local interconnect capacitance, via alignment, thermal coupling, integration risk, and circuit-context delay/energy proxies.

## Data

- Version: 2026-08-21-v82
- Rows: 1728
- Execution: precomputed browser CSV replay only
- Public route: /simulations/cfet-contact-interconnect-parasitic-map
- Lesson route: /learn/cfet-contact-interconnect-parasitic
- Lab route: /labs/cfet-contact-interconnect-parasitic

## Method

The table is an original SemiAgora synthetic sweep. It combines architecture profile, contact scheme, interconnect pitch, via strategy, thermal context, and circuit context into normalized proxy scores. The equations are teaching scaffolds, not calibrated device models.

## Public Boundary

No foundry PDK, TCAD deck, standard-cell layout, CFET process flow, device stack recipe, 3D PEX result, extraction tech file, measured silicon data, or product claim is included. The browser filters saved rows and does not run live TCAD, PEX, SPICE, field solver, or uploaded layout analysis.

## Source Spine

- imec CFET logic roadmap: https://www.imec-int.com/en/articles/imec-puts-complementary-fet-cfet-logic-technology-roadmap
- imec CMOS scaling roadmap: https://www.imec-int.com/en/articles/view-logic-technology-roadmap
- imec nanosheet to forksheet to CFET: https://www.imec-int.com/en/imec-magazine/imec-magazine-december-2019/scaling-cmos-beyond-finfets-from-nanosheets-and-forksheets-to-cfets
- IRDS More Moore 2022: https://irds.ieee.org/images/files/pdf/2022/2022IRDS_MM.pdf
- Synopsys GAA and backside power: https://www.synopsys.com/blogs/chip-design/what-are-gate-all-around-gaa-transistors.html
- Synopsys CFET parasitic variation interview: https://www.synopsys.com/blogs/chip-design/technology-beyond-3nm-interview-jacob-avidan-shankar-krishnamoorthy.html
- Synopsys parasitic extraction glossary: https://www.synopsys.com/glossary/what-is-parasitic-extraction.html