{
  "schema": "semiagora.cfet-contact-interconnect-parasitic-map.v1",
  "version": "2026-08-21-v82",
  "execution_mode": "precomputed_browser_csv_replay_only",
  "source_run": {
    "run_id": "20260821_v82_manual_cfet_source_review",
    "evidence_path": "07_assets/device_lab/experiments/SA-DEV-CFET-001/",
    "rights_mode": "public source links plus original SemiAgora synthetic teaching rows; no vendor NDA, foundry node deck, PDK, TCAD deck, paper body, layout, or measured silicon data"
  },
  "counts": {
    "rows": 1728,
    "architecture_profiles": 4,
    "contact_schemes": 4,
    "interconnect_pitches": 3,
    "via_strategies": 3,
    "thermal_contexts": 3,
    "circuit_contexts": 4,
    "liveServerRuns": 0
  },
  "summary": {
    "decision_gate_counts": {
      "baseline_reference": 348,
      "via_alignment_review": 960,
      "contact_limited": 180,
      "integration_review": 200,
      "thermal_coupling_review": 40
    },
    "architecture_averages": [
      {
        "architecture": "lateral_gaa_reference",
        "rows": 432,
        "mean_density_gain_proxy": "1.044",
        "mean_parasitic_delay_index": "1.002",
        "mean_contact_resistance_index": "1.087",
        "mean_integration_risk_proxy": "0.628",
        "mean_ppa_score_proxy": "0.148"
      },
      {
        "architecture": "forksheet_transition",
        "rows": 432,
        "mean_density_gain_proxy": "1.211",
        "mean_parasitic_delay_index": "0.993",
        "mean_contact_resistance_index": "1.099",
        "mean_integration_risk_proxy": "0.747",
        "mean_ppa_score_proxy": "0.250"
      },
      {
        "architecture": "monolithic_cfet",
        "rows": 432,
        "mean_density_gain_proxy": "1.493",
        "mean_parasitic_delay_index": "1.009",
        "mean_contact_resistance_index": "1.125",
        "mean_integration_risk_proxy": "0.936",
        "mean_ppa_score_proxy": "0.415"
      },
      {
        "architecture": "sequential_cfet",
        "rows": 432,
        "mean_density_gain_proxy": "1.420",
        "mean_parasitic_delay_index": "1.014",
        "mean_contact_resistance_index": "1.118",
        "mean_integration_risk_proxy": "0.903",
        "mean_ppa_score_proxy": "0.355"
      }
    ],
    "top_density_tradeoff_candidates": [
      {
        "case_id": "CFET001-1129",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "backside_source_power_contact",
        "contact_note": "backside access can relieve frontside routing and source resistance while adding via/alignment risk",
        "interconnect_pitch": "tight_m0_m1_pitch",
        "via_strategy": "hybrid_metal_zero_via",
        "thermal_context": "nominal_activity",
        "circuit_context": "inverter_chain",
        "circuit_note": "single-path delay proxy for architecture-to-standard-cell intuition",
        "density_gain_proxy": "1.514",
        "drive_per_footprint_proxy": "1.701",
        "contact_resistance_index": "0.945",
        "local_interconnect_cap_index": "1.125",
        "via_alignment_risk": "0.741",
        "thermal_coupling_risk": "0.581",
        "layout_relief_score": "0.847",
        "parasitic_delay_index": "0.774",
        "energy_index": "0.747",
        "integration_risk_proxy": "0.960",
        "ppa_score_proxy": "0.537",
        "decision_gate": "via_alignment_review",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "review_vertical_alignment_overlay_and_via_stack_assumptions",
        "candidate_note": "high-density candidate, but current gate is via_alignment_review; use as a review queue item, not an architecture win"
      },
      {
        "case_id": "CFET001-1177",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "backside_source_power_contact",
        "contact_note": "backside access can relieve frontside routing and source resistance while adding via/alignment risk",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "backside_via_bridge",
        "thermal_context": "nominal_activity",
        "circuit_context": "inverter_chain",
        "circuit_note": "single-path delay proxy for architecture-to-standard-cell intuition",
        "density_gain_proxy": "1.658",
        "drive_per_footprint_proxy": "1.770",
        "contact_resistance_index": "1.216",
        "local_interconnect_cap_index": "1.292",
        "via_alignment_risk": "0.920",
        "thermal_coupling_risk": "0.581",
        "layout_relief_score": "0.920",
        "parasitic_delay_index": "0.969",
        "energy_index": "0.870",
        "integration_risk_proxy": "0.960",
        "ppa_score_proxy": "0.537",
        "decision_gate": "via_alignment_review",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "review_vertical_alignment_overlay_and_via_stack_assumptions",
        "candidate_note": "high-density candidate, but current gate is via_alignment_review; use as a review queue item, not an architecture win"
      },
      {
        "case_id": "CFET001-1165",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "backside_source_power_contact",
        "contact_note": "backside access can relieve frontside routing and source resistance while adding via/alignment risk",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "hybrid_metal_zero_via",
        "thermal_context": "nominal_activity",
        "circuit_context": "inverter_chain",
        "circuit_note": "single-path delay proxy for architecture-to-standard-cell intuition",
        "density_gain_proxy": "1.647",
        "drive_per_footprint_proxy": "1.763",
        "contact_resistance_index": "1.198",
        "local_interconnect_cap_index": "1.292",
        "via_alignment_risk": "0.777",
        "thermal_coupling_risk": "0.581",
        "layout_relief_score": "0.777",
        "parasitic_delay_index": "0.933",
        "energy_index": "0.856",
        "integration_risk_proxy": "0.960",
        "ppa_score_proxy": "0.533",
        "decision_gate": "via_alignment_review",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "review_vertical_alignment_overlay_and_via_stack_assumptions",
        "candidate_note": "high-density candidate, but current gate is via_alignment_review; use as a review queue item, not an architecture win"
      },
      {
        "case_id": "CFET001-1181",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "backside_source_power_contact",
        "contact_note": "backside access can relieve frontside routing and source resistance while adding via/alignment risk",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "backside_via_bridge",
        "thermal_context": "high_activity",
        "circuit_context": "inverter_chain",
        "circuit_note": "single-path delay proxy for architecture-to-standard-cell intuition",
        "density_gain_proxy": "1.658",
        "drive_per_footprint_proxy": "1.770",
        "contact_resistance_index": "1.216",
        "local_interconnect_cap_index": "1.292",
        "via_alignment_risk": "0.920",
        "thermal_coupling_risk": "0.673",
        "layout_relief_score": "0.920",
        "parasitic_delay_index": "0.983",
        "energy_index": "0.883",
        "integration_risk_proxy": "0.960",
        "ppa_score_proxy": "0.533",
        "decision_gate": "via_alignment_review",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "review_vertical_alignment_overlay_and_via_stack_assumptions",
        "candidate_note": "high-density candidate, but current gate is via_alignment_review; use as a review queue item, not an architecture win"
      },
      {
        "case_id": "CFET001-1133",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "backside_source_power_contact",
        "contact_note": "backside access can relieve frontside routing and source resistance while adding via/alignment risk",
        "interconnect_pitch": "tight_m0_m1_pitch",
        "via_strategy": "hybrid_metal_zero_via",
        "thermal_context": "high_activity",
        "circuit_context": "inverter_chain",
        "circuit_note": "single-path delay proxy for architecture-to-standard-cell intuition",
        "density_gain_proxy": "1.514",
        "drive_per_footprint_proxy": "1.701",
        "contact_resistance_index": "0.945",
        "local_interconnect_cap_index": "1.125",
        "via_alignment_risk": "0.741",
        "thermal_coupling_risk": "0.673",
        "layout_relief_score": "0.847",
        "parasitic_delay_index": "0.788",
        "energy_index": "0.760",
        "integration_risk_proxy": "0.960",
        "ppa_score_proxy": "0.532",
        "decision_gate": "via_alignment_review",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "review_vertical_alignment_overlay_and_via_stack_assumptions",
        "candidate_note": "high-density candidate, but current gate is via_alignment_review; use as a review queue item, not an architecture win"
      },
      {
        "case_id": "CFET001-1137",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "backside_source_power_contact",
        "contact_note": "backside access can relieve frontside routing and source resistance while adding via/alignment risk",
        "interconnect_pitch": "tight_m0_m1_pitch",
        "via_strategy": "hybrid_metal_zero_via",
        "thermal_context": "hotspot_limited",
        "circuit_context": "inverter_chain",
        "circuit_note": "single-path delay proxy for architecture-to-standard-cell intuition",
        "density_gain_proxy": "1.514",
        "drive_per_footprint_proxy": "1.701",
        "contact_resistance_index": "0.945",
        "local_interconnect_cap_index": "1.125",
        "via_alignment_risk": "0.741",
        "thermal_coupling_risk": "0.746",
        "layout_relief_score": "0.847",
        "parasitic_delay_index": "0.800",
        "energy_index": "0.771",
        "integration_risk_proxy": "0.960",
        "ppa_score_proxy": "0.529",
        "decision_gate": "via_alignment_review",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "review_vertical_alignment_overlay_and_via_stack_assumptions",
        "candidate_note": "high-density candidate, but current gate is via_alignment_review; use as a review queue item, not an architecture win"
      },
      {
        "case_id": "CFET001-1185",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "backside_source_power_contact",
        "contact_note": "backside access can relieve frontside routing and source resistance while adding via/alignment risk",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "backside_via_bridge",
        "thermal_context": "hotspot_limited",
        "circuit_context": "inverter_chain",
        "circuit_note": "single-path delay proxy for architecture-to-standard-cell intuition",
        "density_gain_proxy": "1.658",
        "drive_per_footprint_proxy": "1.770",
        "contact_resistance_index": "1.216",
        "local_interconnect_cap_index": "1.292",
        "via_alignment_risk": "0.920",
        "thermal_coupling_risk": "0.746",
        "layout_relief_score": "0.920",
        "parasitic_delay_index": "0.994",
        "energy_index": "0.894",
        "integration_risk_proxy": "0.960",
        "ppa_score_proxy": "0.529",
        "decision_gate": "via_alignment_review",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "review_vertical_alignment_overlay_and_via_stack_assumptions",
        "candidate_note": "high-density candidate, but current gate is via_alignment_review; use as a review queue item, not an architecture win"
      },
      {
        "case_id": "CFET001-1169",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "backside_source_power_contact",
        "contact_note": "backside access can relieve frontside routing and source resistance while adding via/alignment risk",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "hybrid_metal_zero_via",
        "thermal_context": "high_activity",
        "circuit_context": "inverter_chain",
        "circuit_note": "single-path delay proxy for architecture-to-standard-cell intuition",
        "density_gain_proxy": "1.647",
        "drive_per_footprint_proxy": "1.763",
        "contact_resistance_index": "1.198",
        "local_interconnect_cap_index": "1.292",
        "via_alignment_risk": "0.777",
        "thermal_coupling_risk": "0.673",
        "layout_relief_score": "0.777",
        "parasitic_delay_index": "0.947",
        "energy_index": "0.869",
        "integration_risk_proxy": "0.960",
        "ppa_score_proxy": "0.528",
        "decision_gate": "via_alignment_review",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "review_vertical_alignment_overlay_and_via_stack_assumptions",
        "candidate_note": "high-density candidate, but current gate is via_alignment_review; use as a review queue item, not an architecture win"
      },
      {
        "case_id": "CFET001-1141",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "backside_source_power_contact",
        "contact_note": "backside access can relieve frontside routing and source resistance while adding via/alignment risk",
        "interconnect_pitch": "tight_m0_m1_pitch",
        "via_strategy": "backside_via_bridge",
        "thermal_context": "nominal_activity",
        "circuit_context": "inverter_chain",
        "circuit_note": "single-path delay proxy for architecture-to-standard-cell intuition",
        "density_gain_proxy": "1.525",
        "drive_per_footprint_proxy": "1.710",
        "contact_resistance_index": "0.959",
        "local_interconnect_cap_index": "1.125",
        "via_alignment_risk": "0.920",
        "thermal_coupling_risk": "0.581",
        "layout_relief_score": "0.920",
        "parasitic_delay_index": "0.816",
        "energy_index": "0.763",
        "integration_risk_proxy": "0.960",
        "ppa_score_proxy": "0.525",
        "decision_gate": "via_alignment_review",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "review_vertical_alignment_overlay_and_via_stack_assumptions",
        "candidate_note": "high-density candidate, but current gate is via_alignment_review; use as a review queue item, not an architecture win"
      },
      {
        "case_id": "CFET001-1173",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "backside_source_power_contact",
        "contact_note": "backside access can relieve frontside routing and source resistance while adding via/alignment risk",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "hybrid_metal_zero_via",
        "thermal_context": "hotspot_limited",
        "circuit_context": "inverter_chain",
        "circuit_note": "single-path delay proxy for architecture-to-standard-cell intuition",
        "density_gain_proxy": "1.647",
        "drive_per_footprint_proxy": "1.763",
        "contact_resistance_index": "1.198",
        "local_interconnect_cap_index": "1.292",
        "via_alignment_risk": "0.777",
        "thermal_coupling_risk": "0.746",
        "layout_relief_score": "0.777",
        "parasitic_delay_index": "0.959",
        "energy_index": "0.879",
        "integration_risk_proxy": "0.960",
        "ppa_score_proxy": "0.524",
        "decision_gate": "via_alignment_review",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "review_vertical_alignment_overlay_and_via_stack_assumptions",
        "candidate_note": "high-density candidate, but current gate is via_alignment_review; use as a review queue item, not an architecture win"
      },
      {
        "case_id": "CFET001-1145",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "backside_source_power_contact",
        "contact_note": "backside access can relieve frontside routing and source resistance while adding via/alignment risk",
        "interconnect_pitch": "tight_m0_m1_pitch",
        "via_strategy": "backside_via_bridge",
        "thermal_context": "high_activity",
        "circuit_context": "inverter_chain",
        "circuit_note": "single-path delay proxy for architecture-to-standard-cell intuition",
        "density_gain_proxy": "1.525",
        "drive_per_footprint_proxy": "1.710",
        "contact_resistance_index": "0.959",
        "local_interconnect_cap_index": "1.125",
        "via_alignment_risk": "0.920",
        "thermal_coupling_risk": "0.673",
        "layout_relief_score": "0.920",
        "parasitic_delay_index": "0.830",
        "energy_index": "0.777",
        "integration_risk_proxy": "0.960",
        "ppa_score_proxy": "0.520",
        "decision_gate": "via_alignment_review",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "review_vertical_alignment_overlay_and_via_stack_assumptions",
        "candidate_note": "high-density candidate, but current gate is via_alignment_review; use as a review queue item, not an architecture win"
      },
      {
        "case_id": "CFET001-1149",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "backside_source_power_contact",
        "contact_note": "backside access can relieve frontside routing and source resistance while adding via/alignment risk",
        "interconnect_pitch": "tight_m0_m1_pitch",
        "via_strategy": "backside_via_bridge",
        "thermal_context": "hotspot_limited",
        "circuit_context": "inverter_chain",
        "circuit_note": "single-path delay proxy for architecture-to-standard-cell intuition",
        "density_gain_proxy": "1.525",
        "drive_per_footprint_proxy": "1.710",
        "contact_resistance_index": "0.959",
        "local_interconnect_cap_index": "1.125",
        "via_alignment_risk": "0.920",
        "thermal_coupling_risk": "0.746",
        "layout_relief_score": "0.920",
        "parasitic_delay_index": "0.841",
        "energy_index": "0.787",
        "integration_risk_proxy": "0.960",
        "ppa_score_proxy": "0.517",
        "decision_gate": "via_alignment_review",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "review_vertical_alignment_overlay_and_via_stack_assumptions",
        "candidate_note": "high-density candidate, but current gate is via_alignment_review; use as a review queue item, not an architecture win"
      }
    ],
    "most_contact_limited_rows": [
      {
        "case_id": "CFET001-0937",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "frontside_mol_reference",
        "contact_note": "reference contact stack that keeps access familiar but routing pressure visible",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "conventional_via_stack",
        "thermal_context": "nominal_activity",
        "circuit_context": "inverter_chain",
        "circuit_note": "single-path delay proxy for architecture-to-standard-cell intuition",
        "density_gain_proxy": "1.608",
        "drive_per_footprint_proxy": "1.598",
        "contact_resistance_index": "1.631",
        "local_interconnect_cap_index": "1.368",
        "via_alignment_risk": "0.527",
        "thermal_coupling_risk": "0.581",
        "layout_relief_score": "0.257",
        "parasitic_delay_index": "1.105",
        "energy_index": "0.930",
        "integration_risk_proxy": "0.887",
        "ppa_score_proxy": "0.390",
        "decision_gate": "contact_limited",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "attach_contact_resistance_and_mol_variation_evidence"
      },
      {
        "case_id": "CFET001-0938",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "frontside_mol_reference",
        "contact_note": "reference contact stack that keeps access familiar but routing pressure visible",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "conventional_via_stack",
        "thermal_context": "nominal_activity",
        "circuit_context": "local_clock_buffer",
        "circuit_note": "clock paths expose capacitance, slew, and power sensitivity",
        "density_gain_proxy": "1.608",
        "drive_per_footprint_proxy": "1.597",
        "contact_resistance_index": "1.631",
        "local_interconnect_cap_index": "1.377",
        "via_alignment_risk": "0.527",
        "thermal_coupling_risk": "0.594",
        "layout_relief_score": "0.257",
        "parasitic_delay_index": "1.394",
        "energy_index": "1.240",
        "integration_risk_proxy": "0.887",
        "ppa_score_proxy": "0.289",
        "decision_gate": "contact_limited",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "attach_contact_resistance_and_mol_variation_evidence"
      },
      {
        "case_id": "CFET001-0939",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "frontside_mol_reference",
        "contact_note": "reference contact stack that keeps access familiar but routing pressure visible",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "conventional_via_stack",
        "thermal_context": "nominal_activity",
        "circuit_context": "sram_edge_peripheral",
        "circuit_note": "memory-edge logic highlights local routing and contact access pressure",
        "density_gain_proxy": "1.608",
        "drive_per_footprint_proxy": "1.597",
        "contact_resistance_index": "1.631",
        "local_interconnect_cap_index": "1.375",
        "via_alignment_risk": "0.527",
        "thermal_coupling_risk": "0.587",
        "layout_relief_score": "0.257",
        "parasitic_delay_index": "1.263",
        "energy_index": "1.074",
        "integration_risk_proxy": "0.887",
        "ppa_score_proxy": "0.338",
        "decision_gate": "contact_limited",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "attach_contact_resistance_and_mol_variation_evidence"
      },
      {
        "case_id": "CFET001-0940",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "frontside_mol_reference",
        "contact_note": "reference contact stack that keeps access familiar but routing pressure visible",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "conventional_via_stack",
        "thermal_context": "nominal_activity",
        "circuit_context": "dense_datapath_cell",
        "circuit_note": "density benefit matters only if parasitics do not erase it",
        "density_gain_proxy": "1.608",
        "drive_per_footprint_proxy": "1.598",
        "contact_resistance_index": "1.631",
        "local_interconnect_cap_index": "1.371",
        "via_alignment_risk": "0.527",
        "thermal_coupling_risk": "0.585",
        "layout_relief_score": "0.257",
        "parasitic_delay_index": "1.183",
        "energy_index": "1.025",
        "integration_risk_proxy": "0.887",
        "ppa_score_proxy": "0.361",
        "decision_gate": "contact_limited",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "attach_contact_resistance_and_mol_variation_evidence"
      },
      {
        "case_id": "CFET001-0941",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "frontside_mol_reference",
        "contact_note": "reference contact stack that keeps access familiar but routing pressure visible",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "conventional_via_stack",
        "thermal_context": "high_activity",
        "circuit_context": "inverter_chain",
        "circuit_note": "single-path delay proxy for architecture-to-standard-cell intuition",
        "density_gain_proxy": "1.608",
        "drive_per_footprint_proxy": "1.598",
        "contact_resistance_index": "1.631",
        "local_interconnect_cap_index": "1.368",
        "via_alignment_risk": "0.527",
        "thermal_coupling_risk": "0.673",
        "layout_relief_score": "0.257",
        "parasitic_delay_index": "1.119",
        "energy_index": "0.943",
        "integration_risk_proxy": "0.907",
        "ppa_score_proxy": "0.382",
        "decision_gate": "contact_limited",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "attach_contact_resistance_and_mol_variation_evidence"
      },
      {
        "case_id": "CFET001-0942",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "frontside_mol_reference",
        "contact_note": "reference contact stack that keeps access familiar but routing pressure visible",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "conventional_via_stack",
        "thermal_context": "high_activity",
        "circuit_context": "local_clock_buffer",
        "circuit_note": "clock paths expose capacitance, slew, and power sensitivity",
        "density_gain_proxy": "1.608",
        "drive_per_footprint_proxy": "1.597",
        "contact_resistance_index": "1.631",
        "local_interconnect_cap_index": "1.377",
        "via_alignment_risk": "0.527",
        "thermal_coupling_risk": "0.686",
        "layout_relief_score": "0.257",
        "parasitic_delay_index": "1.412",
        "energy_index": "1.257",
        "integration_risk_proxy": "0.907",
        "ppa_score_proxy": "0.280",
        "decision_gate": "contact_limited",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "attach_contact_resistance_and_mol_variation_evidence"
      },
      {
        "case_id": "CFET001-0943",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "frontside_mol_reference",
        "contact_note": "reference contact stack that keeps access familiar but routing pressure visible",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "conventional_via_stack",
        "thermal_context": "high_activity",
        "circuit_context": "sram_edge_peripheral",
        "circuit_note": "memory-edge logic highlights local routing and contact access pressure",
        "density_gain_proxy": "1.608",
        "drive_per_footprint_proxy": "1.597",
        "contact_resistance_index": "1.631",
        "local_interconnect_cap_index": "1.375",
        "via_alignment_risk": "0.527",
        "thermal_coupling_risk": "0.679",
        "layout_relief_score": "0.257",
        "parasitic_delay_index": "1.279",
        "energy_index": "1.089",
        "integration_risk_proxy": "0.907",
        "ppa_score_proxy": "0.329",
        "decision_gate": "contact_limited",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "attach_contact_resistance_and_mol_variation_evidence"
      },
      {
        "case_id": "CFET001-0944",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "frontside_mol_reference",
        "contact_note": "reference contact stack that keeps access familiar but routing pressure visible",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "conventional_via_stack",
        "thermal_context": "high_activity",
        "circuit_context": "dense_datapath_cell",
        "circuit_note": "density benefit matters only if parasitics do not erase it",
        "density_gain_proxy": "1.608",
        "drive_per_footprint_proxy": "1.598",
        "contact_resistance_index": "1.631",
        "local_interconnect_cap_index": "1.371",
        "via_alignment_risk": "0.527",
        "thermal_coupling_risk": "0.677",
        "layout_relief_score": "0.257",
        "parasitic_delay_index": "1.199",
        "energy_index": "1.039",
        "integration_risk_proxy": "0.907",
        "ppa_score_proxy": "0.353",
        "decision_gate": "contact_limited",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "attach_contact_resistance_and_mol_variation_evidence"
      },
      {
        "case_id": "CFET001-0945",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "frontside_mol_reference",
        "contact_note": "reference contact stack that keeps access familiar but routing pressure visible",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "conventional_via_stack",
        "thermal_context": "hotspot_limited",
        "circuit_context": "inverter_chain",
        "circuit_note": "single-path delay proxy for architecture-to-standard-cell intuition",
        "density_gain_proxy": "1.608",
        "drive_per_footprint_proxy": "1.598",
        "contact_resistance_index": "1.631",
        "local_interconnect_cap_index": "1.368",
        "via_alignment_risk": "0.527",
        "thermal_coupling_risk": "0.746",
        "layout_relief_score": "0.257",
        "parasitic_delay_index": "1.130",
        "energy_index": "0.954",
        "integration_risk_proxy": "0.935",
        "ppa_score_proxy": "0.374",
        "decision_gate": "contact_limited",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "attach_contact_resistance_and_mol_variation_evidence"
      },
      {
        "case_id": "CFET001-0946",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "frontside_mol_reference",
        "contact_note": "reference contact stack that keeps access familiar but routing pressure visible",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "conventional_via_stack",
        "thermal_context": "hotspot_limited",
        "circuit_context": "local_clock_buffer",
        "circuit_note": "clock paths expose capacitance, slew, and power sensitivity",
        "density_gain_proxy": "1.608",
        "drive_per_footprint_proxy": "1.597",
        "contact_resistance_index": "1.631",
        "local_interconnect_cap_index": "1.377",
        "via_alignment_risk": "0.527",
        "thermal_coupling_risk": "0.759",
        "layout_relief_score": "0.257",
        "parasitic_delay_index": "1.426",
        "energy_index": "1.271",
        "integration_risk_proxy": "0.935",
        "ppa_score_proxy": "0.270",
        "decision_gate": "contact_limited",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "attach_contact_resistance_and_mol_variation_evidence"
      },
      {
        "case_id": "CFET001-0947",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "frontside_mol_reference",
        "contact_note": "reference contact stack that keeps access familiar but routing pressure visible",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "conventional_via_stack",
        "thermal_context": "hotspot_limited",
        "circuit_context": "sram_edge_peripheral",
        "circuit_note": "memory-edge logic highlights local routing and contact access pressure",
        "density_gain_proxy": "1.608",
        "drive_per_footprint_proxy": "1.597",
        "contact_resistance_index": "1.631",
        "local_interconnect_cap_index": "1.375",
        "via_alignment_risk": "0.527",
        "thermal_coupling_risk": "0.752",
        "layout_relief_score": "0.257",
        "parasitic_delay_index": "1.292",
        "energy_index": "1.101",
        "integration_risk_proxy": "0.935",
        "ppa_score_proxy": "0.320",
        "decision_gate": "contact_limited",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "attach_contact_resistance_and_mol_variation_evidence"
      },
      {
        "case_id": "CFET001-0948",
        "architecture": "monolithic_cfet",
        "architecture_note": "stacked n/p devices improve footprint but raise high-aspect-ratio and contact-patterning burden",
        "contact_scheme": "frontside_mol_reference",
        "contact_note": "reference contact stack that keeps access familiar but routing pressure visible",
        "interconnect_pitch": "extreme_track_scaling",
        "via_strategy": "conventional_via_stack",
        "thermal_context": "hotspot_limited",
        "circuit_context": "dense_datapath_cell",
        "circuit_note": "density benefit matters only if parasitics do not erase it",
        "density_gain_proxy": "1.608",
        "drive_per_footprint_proxy": "1.598",
        "contact_resistance_index": "1.631",
        "local_interconnect_cap_index": "1.371",
        "via_alignment_risk": "0.527",
        "thermal_coupling_risk": "0.750",
        "layout_relief_score": "0.257",
        "parasitic_delay_index": "1.211",
        "energy_index": "1.051",
        "integration_risk_proxy": "0.935",
        "ppa_score_proxy": "0.344",
        "decision_gate": "contact_limited",
        "evidence_state": "review_before_architecture_claim",
        "next_safe_check": "attach_contact_resistance_and_mol_variation_evidence"
      }
    ]
  },
  "role_views": [
    {
      "role": "device engineer",
      "reads": [
        "architecture",
        "drive_per_footprint_proxy",
        "thermal_coupling_risk",
        "decision_gate"
      ],
      "use": "Separate stacked-device density from electrostatic, thermal, and contact access penalties before ranking architectures."
    },
    {
      "role": "process integration",
      "reads": [
        "contact_scheme",
        "via_strategy",
        "via_alignment_risk",
        "integration_risk_proxy"
      ],
      "use": "Treat contacts, backside access, and via bridges as integration-review items, not generic device features."
    },
    {
      "role": "circuit designer",
      "reads": [
        "circuit_context",
        "parasitic_delay_index",
        "energy_index",
        "ppa_score_proxy"
      ],
      "use": "Check whether contact and interconnect parasitics erase the density or drive benefit in a circuit context."
    },
    {
      "role": "layout and extraction",
      "reads": [
        "interconnect_pitch",
        "local_interconnect_cap_index",
        "layout_relief_score",
        "next_safe_check"
      ],
      "use": "Ask for 3D PEX, route-access, and variation evidence before reusing the row in a timing or area claim."
    }
  ],
  "methods": [
    "Cartesian sweep across architecture profile, contact scheme, local interconnect pitch, via strategy, thermal context, and circuit context.",
    "Normalized proxy equations convert public CFET/GAA/MOL/BEOL vocabulary into density, drive, contact resistance, capacitance, delay, energy, thermal, integration, and PPA scores.",
    "Decision gates prioritize contact resistance, via alignment, thermal coupling, and integration review before labeling a density tradeoff promising.",
    "Rows are original synthetic teaching data and require rights-cleared measured replacement evidence before stronger engineering use."
  ],
  "public_boundary": [
    "No foundry PDK, TCAD deck, standard-cell layout, CFET process flow, vendor roadmap table, device stack recipe, 3D PEX result, extraction tech file, or measured silicon data is included.",
    "No live server TCAD, PEX, SPICE, field solver, layout upload, model ingestion, account, payment, comment, newsletter signup, job/event workflow, or public service intake is enabled.",
    "No node ranking, product readiness, timing signoff, density guarantee, reliability qualification, foundry roadmap claim, or process integration approval is made."
  ],
  "sources": [
    {
      "label": "imec CFET logic roadmap",
      "url": "https://www.imec-int.com/en/articles/imec-puts-complementary-fet-cfet-logic-technology-roadmap",
      "note": "Public source for CFET as vertically stacked nMOS/pMOS, monolithic and sequential schemes, PPAC framing, and contact-patterning challenge vocabulary."
    },
    {
      "label": "imec CMOS scaling roadmap",
      "url": "https://www.imec-int.com/en/articles/view-logic-technology-roadmap",
      "note": "Public source for FEOL/MOL/BEOL, contact resistance, local interconnect, via, BPR, and routing-congestion vocabulary."
    },
    {
      "label": "imec nanosheet to forksheet to CFET",
      "url": "https://www.imec-int.com/en/imec-magazine/imec-magazine-december-2019/scaling-cmos-beyond-finfets-from-nanosheets-and-forksheets-to-cfets",
      "note": "Public source for CFET two-level local-interconnect and cell-area/routability teaching language."
    },
    {
      "label": "IRDS More Moore 2022",
      "url": "https://irds.ieee.org/images/files/pdf/2022/2022IRDS_MM.pdf",
      "note": "Roadmap source for drive-per-footprint, parasitics, contact engineering, device stacking, and PPAC tradeoff framing."
    },
    {
      "label": "Synopsys GAA and backside power",
      "url": "https://www.synopsys.com/blogs/chip-design/what-are-gate-all-around-gaa-transistors.html",
      "note": "Public source for GAA context and backside power distribution as a routing and resistance relief concept."
    },
    {
      "label": "Synopsys CFET parasitic variation interview",
      "url": "https://www.synopsys.com/blogs/chip-design/technology-beyond-3nm-interview-jacob-avidan-shankar-krishnamoorthy.html",
      "note": "Public source for CFET parasitic variation, MOL/interconnect variation, and early PPA modeling language."
    },
    {
      "label": "Synopsys parasitic extraction glossary",
      "url": "https://www.synopsys.com/glossary/what-is-parasitic-extraction.html",
      "note": "Public source defining FEOL, MEOL/contact, and BEOL/interconnect parasitics and extraction boundaries."
    }
  ]
}