{
  "schema": "semiagora.github-seed-simulation.v1",
  "execution_mode": "precomputed-only",
  "experiment_id": "SA-SEED-MEM-DRAM-HBM-BANK-001",
  "slug": "dram-hbm-row-buffer-bank-parallelism",
  "title": "DRAM/HBM row-buffer and bank parallelism",
  "model_boundary": "normalized educational memory-system replay, not a JEDEC timing model",
  "public_boundary": [
    "No live server solver execution.",
    "No PDK or compact-model ingestion.",
    "No process recipe, equipment operation, qualification signoff, upload, account, payment, comment, newsletter signup, or submission workflow.",
    "Third-party GitHub tools remain source links unless separately reviewed."
  ],
  "headline_metric": {
    "name": "best_throughput_index",
    "value": 1.60578,
    "case": {
      "banks": 32,
      "row_hit_rate": 0.9
    }
  },
  "rows": [
    {
      "simulation_id": "SA-SEED-MEM-DRAM-HBM-BANK-001",
      "domain": "memory",
      "banks": 8,
      "row_hit_rate": 0.45,
      "avg_latency_ns": 21.9481,
      "throughput_index": 0.14979,
      "teaching_point": "Row-buffer locality and bank-level parallelism matter before raw bandwidth does."
    },
    {
      "simulation_id": "SA-SEED-MEM-DRAM-HBM-BANK-001",
      "domain": "memory",
      "banks": 8,
      "row_hit_rate": 0.6,
      "avg_latency_ns": 18.8127,
      "throughput_index": 0.1887,
      "teaching_point": "Row-buffer locality and bank-level parallelism matter before raw bandwidth does."
    },
    {
      "simulation_id": "SA-SEED-MEM-DRAM-HBM-BANK-001",
      "domain": "memory",
      "banks": 8,
      "row_hit_rate": 0.75,
      "avg_latency_ns": 15.6772,
      "throughput_index": 0.24319,
      "teaching_point": "Row-buffer locality and bank-level parallelism matter before raw bandwidth does."
    },
    {
      "simulation_id": "SA-SEED-MEM-DRAM-HBM-BANK-001",
      "domain": "memory",
      "banks": 8,
      "row_hit_rate": 0.9,
      "avg_latency_ns": 12.5418,
      "throughput_index": 0.32491,
      "teaching_point": "Row-buffer locality and bank-level parallelism matter before raw bandwidth does."
    },
    {
      "simulation_id": "SA-SEED-MEM-DRAM-HBM-BANK-001",
      "domain": "memory",
      "banks": 16,
      "row_hit_rate": 0.45,
      "avg_latency_ns": 20.9016,
      "throughput_index": 0.34088,
      "teaching_point": "Row-buffer locality and bank-level parallelism matter before raw bandwidth does."
    },
    {
      "simulation_id": "SA-SEED-MEM-DRAM-HBM-BANK-001",
      "domain": "memory",
      "banks": 16,
      "row_hit_rate": 0.6,
      "avg_latency_ns": 17.9156,
      "throughput_index": 0.427,
      "teaching_point": "Row-buffer locality and bank-level parallelism matter before raw bandwidth does."
    },
    {
      "simulation_id": "SA-SEED-MEM-DRAM-HBM-BANK-001",
      "domain": "memory",
      "banks": 16,
      "row_hit_rate": 0.75,
      "avg_latency_ns": 14.9297,
      "throughput_index": 0.54757,
      "teaching_point": "Row-buffer locality and bank-level parallelism matter before raw bandwidth does."
    },
    {
      "simulation_id": "SA-SEED-MEM-DRAM-HBM-BANK-001",
      "domain": "memory",
      "banks": 16,
      "row_hit_rate": 0.9,
      "avg_latency_ns": 11.9437,
      "throughput_index": 0.72841,
      "teaching_point": "Row-buffer locality and bank-level parallelism matter before raw bandwidth does."
    },
    {
      "simulation_id": "SA-SEED-MEM-DRAM-HBM-BANK-001",
      "domain": "memory",
      "banks": 32,
      "row_hit_rate": 0.45,
      "avg_latency_ns": 20.1615,
      "throughput_index": 0.76135,
      "teaching_point": "Row-buffer locality and bank-level parallelism matter before raw bandwidth does."
    },
    {
      "simulation_id": "SA-SEED-MEM-DRAM-HBM-BANK-001",
      "domain": "memory",
      "banks": 32,
      "row_hit_rate": 0.6,
      "avg_latency_ns": 17.2813,
      "throughput_index": 0.949,
      "teaching_point": "Row-buffer locality and bank-level parallelism matter before raw bandwidth does."
    },
    {
      "simulation_id": "SA-SEED-MEM-DRAM-HBM-BANK-001",
      "domain": "memory",
      "banks": 32,
      "row_hit_rate": 0.75,
      "avg_latency_ns": 14.4011,
      "throughput_index": 1.21171,
      "teaching_point": "Row-buffer locality and bank-level parallelism matter before raw bandwidth does."
    },
    {
      "simulation_id": "SA-SEED-MEM-DRAM-HBM-BANK-001",
      "domain": "memory",
      "banks": 32,
      "row_hit_rate": 0.9,
      "avg_latency_ns": 11.5209,
      "throughput_index": 1.60578,
      "teaching_point": "Row-buffer locality and bank-level parallelism matter before raw bandwidth does."
    }
  ],
  "methods": [
    "Average hit and miss cycles are blended by row-hit rate and adjusted by a bank-conflict proxy.",
    "Throughput index combines bank count, efficiency, and average cycle cost.",
    "The row-hit and bank axes are intentionally normalized for classroom comparison."
  ],
  "limitations": [
    "Not a cycle-accurate DRAM, HBM, controller, refresh, thermal, or RowHammer model.",
    "No JEDEC timing table, commercial memory configuration, or measured trace is included.",
    "Research-grade studies should use Ramulator2, DRAMsim3, or measured traces after setup review."
  ],
  "evidence": [
    "Seed sweep JSON records every row and the best throughput-index case.",
    "CSV export preserves the row-hit, bank-count, latency, and throughput columns.",
    "GitHub expedition note records Ramulator2 and DRAMsim3 as external solver references."
  ],
  "sources": [
    {
      "label": "Ramulator2",
      "url": "https://github.com/CMU-SAFARI/ramulator2",
      "note": "External MIT-licensed DRAM/HBM memory-system simulator reference; SemiAgora page uses original precomputed teaching data."
    },
    {
      "label": "DRAMsim3",
      "url": "https://github.com/umd-memsys/DRAMsim3",
      "note": "External MIT-licensed DRAM timing and thermal-capable simulator reference."
    }
  ],
  "source_seed_run": "07_assets/factory_lab/experiments/GITHUB_OPEN_SOURCE_SEED_SWEEP_2026-08-14/"
}