{
  "schema": "semiagora.emerging-memory-placement-reliability.v1",
  "version": "2026-08-22-v86",
  "experiment_id": "SA-MEM-EMERGING-TAXONOMY-003",
  "slug": "emerging-memory-placement-reliability-map",
  "route": "/simulations/emerging-memory-placement-reliability-map",
  "lesson_route": "/learn/emerging-memory-placement-reliability",
  "lab_route": "/labs/emerging-memory-placement-reliability",
  "title": "Emerging memory placement and reliability map",
  "execution_mode": "precomputed_browser_csv_replay_only",
  "counts": {
    "rows": 1728,
    "memory_technologies": 12,
    "placement_targets": 4,
    "integration_contexts": 4,
    "workload_contexts": 3,
    "decision_priorities": 3,
    "liveServerRuns": 0
  },
  "source_summary": "Public source anchors were used link-first for vocabulary and taxonomy only. SemiAgora generated original synthetic teaching rows and did not copy article bodies, paper figures, tables, product claims, course material, or code.",
  "sources": [
    {
      "label": "Purdue Semiconductor Memory 101",
      "url": "https://engineering.purdue.edu/online/semiconductors/semiconductor-memory-101",
      "note": "Public memory-course anchor for SRAM, DRAM, Flash, emerging memories, hierarchy, reliability, packaging, and system-level memory management."
    },
    {
      "label": "Purdue Semiconductor Memory Technologies and Applications",
      "url": "https://engineering.purdue.edu/online/courses/tagged_items/semiconductor-memory-technologies-and-applications",
      "note": "Public course description anchor for SRAM, DRAM, eDRAM, 3D HBM, Flash, RRAM, PCM, MRAM, and FeRAM/FeFET coverage."
    },
    {
      "label": "imec active memory overview",
      "url": "https://www.imec-int.com/en/expertise/cmos-advanced/store/memory",
      "note": "Public DRAM, active-memory, and memory-wall vocabulary anchor used link-first only."
    },
    {
      "label": "imec ferroelectric memory research",
      "url": "https://www.imec-int.com/en/press/imec-achieves-breakthroughs-ferroelectric-memory-research-next-generation-memory-solutions",
      "note": "Public FeFET/ferroelectric memory signal used for vocabulary only, not as a process or product calibration."
    },
    {
      "label": "imec MRAM technologies",
      "url": "https://www.imec-int.com/en/articles/mram-technologies-space-applications-unified-cache-memory",
      "note": "Public MRAM overview for MTJ, STT/SOT, and placement vocabulary without copying figures or product claims."
    },
    {
      "label": "InMRAM introductory course metadata",
      "url": "https://arxiv.org/abs/1906.10206",
      "note": "Public MRAM course metadata/source anchor for magnetism and spintronics vocabulary; no course material is copied."
    },
    {
      "label": "Overview of emerging nonvolatile memory technologies",
      "url": "https://pmc.ncbi.nlm.nih.gov/articles/PMC4182445/",
      "note": "Open-access review anchor for high-level NVM categories; SemiAgora does not copy review tables or figures."
    },
    {
      "label": "Progress of emerging non-volatile memory technologies",
      "url": "https://link.springer.com/article/10.1557/s43579-024-00660-2",
      "note": "Public review metadata/source anchor for FeRAM, PCM, RRAM, and MRAM trend vocabulary; used link-first only."
    }
  ],
  "axes": {
    "memory_technologies": [
      {
        "id": "sram_cache",
        "label": "SRAM cache",
        "volatility": 1,
        "latency": 0.95,
        "density": 0.24,
        "endurance": 0.96,
        "retention": 0.2,
        "writeEnergy": 0.42,
        "readMarginRisk": 0.26,
        "processCompatibility": 0.9,
        "integrationRisk": 0.18,
        "maturity": 0.98,
        "thermalRisk": 0.3,
        "note": "fast volatile baseline for near-logic placement"
      },
      {
        "id": "planar_dram",
        "label": "Planar DRAM",
        "volatility": 1,
        "latency": 0.7,
        "density": 0.78,
        "endurance": 0.92,
        "retention": 0.48,
        "writeEnergy": 0.4,
        "readMarginRisk": 0.38,
        "processCompatibility": 0.78,
        "integrationRisk": 0.34,
        "maturity": 0.96,
        "thermalRisk": 0.5,
        "note": "main-memory baseline with refresh and cell-tail evidence"
      },
      {
        "id": "hbm_3d_dram",
        "label": "HBM / 3D DRAM",
        "volatility": 1,
        "latency": 0.66,
        "density": 0.86,
        "endurance": 0.9,
        "retention": 0.44,
        "writeEnergy": 0.36,
        "readMarginRisk": 0.42,
        "processCompatibility": 0.74,
        "integrationRisk": 0.62,
        "maturity": 0.86,
        "thermalRisk": 0.68,
        "note": "stacked DRAM emphasizes bandwidth, package, and thermal evidence"
      },
      {
        "id": "3d_nand_flash",
        "label": "3D NAND Flash",
        "volatility": 0,
        "latency": 0.18,
        "density": 0.98,
        "endurance": 0.32,
        "retention": 0.76,
        "writeEnergy": 0.76,
        "readMarginRisk": 0.64,
        "processCompatibility": 0.72,
        "integrationRisk": 0.56,
        "maturity": 0.94,
        "thermalRisk": 0.48,
        "note": "storage-density anchor with threshold, ECC, and retention evidence"
      },
      {
        "id": "edram_mimcap",
        "label": "eDRAM / MIMCAP",
        "volatility": 1,
        "latency": 0.62,
        "density": 0.6,
        "endurance": 0.86,
        "retention": 0.4,
        "writeEnergy": 0.38,
        "readMarginRisk": 0.44,
        "processCompatibility": 0.62,
        "integrationRisk": 0.5,
        "maturity": 0.66,
        "thermalRisk": 0.46,
        "note": "embedded density option with refresh and capacitor integration burden"
      },
      {
        "id": "stt_sot_mram",
        "label": "STT/SOT-MRAM",
        "volatility": 0,
        "latency": 0.7,
        "density": 0.52,
        "endurance": 0.72,
        "retention": 0.9,
        "writeEnergy": 0.6,
        "readMarginRisk": 0.54,
        "processCompatibility": 0.7,
        "integrationRisk": 0.52,
        "maturity": 0.72,
        "thermalRisk": 0.44,
        "note": "nonvolatile embedded candidate with switching, read margin, retention, and disturb tradeoffs"
      },
      {
        "id": "fefet_feram",
        "label": "FeFET / FeRAM",
        "volatility": 0,
        "latency": 0.62,
        "density": 0.56,
        "endurance": 0.5,
        "retention": 0.72,
        "writeEnergy": 0.4,
        "readMarginRisk": 0.58,
        "processCompatibility": 0.58,
        "integrationRisk": 0.66,
        "maturity": 0.52,
        "thermalRisk": 0.42,
        "note": "ferroelectric path with wake-up, fatigue, erase, and integration questions"
      },
      {
        "id": "reram_rram",
        "label": "ReRAM / RRAM",
        "volatility": 0,
        "latency": 0.5,
        "density": 0.72,
        "endurance": 0.44,
        "retention": 0.68,
        "writeEnergy": 0.52,
        "readMarginRisk": 0.7,
        "processCompatibility": 0.62,
        "integrationRisk": 0.62,
        "maturity": 0.56,
        "thermalRisk": 0.5,
        "note": "filamentary memory needs variability and forming/reset evidence"
      },
      {
        "id": "pcm_pram",
        "label": "PCM / PRAM",
        "volatility": 0,
        "latency": 0.38,
        "density": 0.68,
        "endurance": 0.38,
        "retention": 0.7,
        "writeEnergy": 0.82,
        "readMarginRisk": 0.66,
        "processCompatibility": 0.56,
        "integrationRisk": 0.64,
        "maturity": 0.58,
        "thermalRisk": 0.76,
        "note": "phase-change memory emphasizes write heat, drift, and read-margin evidence"
      },
      {
        "id": "scm_cxl_memory",
        "label": "SCM / CXL memory tier",
        "volatility": 0.15,
        "latency": 0.46,
        "density": 0.76,
        "endurance": 0.48,
        "retention": 0.72,
        "writeEnergy": 0.64,
        "readMarginRisk": 0.6,
        "processCompatibility": 0.64,
        "integrationRisk": 0.7,
        "maturity": 0.5,
        "thermalRisk": 0.58,
        "note": "system-tier placement rather than a single cell technology claim"
      },
      {
        "id": "embedded_nvm",
        "label": "Embedded NVM",
        "volatility": 0,
        "latency": 0.4,
        "density": 0.44,
        "endurance": 0.48,
        "retention": 0.84,
        "writeEnergy": 0.56,
        "readMarginRisk": 0.5,
        "processCompatibility": 0.76,
        "integrationRisk": 0.44,
        "maturity": 0.78,
        "thermalRisk": 0.34,
        "note": "code/storage option where qualification and process compatibility dominate"
      },
      {
        "id": "cim_crossbar",
        "label": "CIM crossbar memory",
        "volatility": 0.05,
        "latency": 0.56,
        "density": 0.7,
        "endurance": 0.4,
        "retention": 0.62,
        "writeEnergy": 0.58,
        "readMarginRisk": 0.78,
        "processCompatibility": 0.48,
        "integrationRisk": 0.78,
        "maturity": 0.38,
        "thermalRisk": 0.58,
        "note": "compute-in-memory candidate with analog accuracy, variability, and mapping limits"
      }
    ],
    "placement_targets": [
      {
        "id": "near_logic_cache",
        "label": "Near-logic cache or scratchpad",
        "latencyWeight": 0.36,
        "densityWeight": 0.12,
        "enduranceWeight": 0.18,
        "retentionWeight": 0.08,
        "energyWeight": 0.18,
        "compatibilityWeight": 0.08,
        "integrationPenalty": 0.18,
        "note": "latency and logic compatibility dominate"
      },
      {
        "id": "embedded_code_config",
        "label": "Embedded code/config memory",
        "latencyWeight": 0.12,
        "densityWeight": 0.16,
        "enduranceWeight": 0.16,
        "retentionWeight": 0.34,
        "energyWeight": 0.1,
        "compatibilityWeight": 0.12,
        "integrationPenalty": 0.14,
        "note": "retention, maturity, and process compatibility dominate"
      },
      {
        "id": "main_near_memory",
        "label": "Main or near-memory tier",
        "latencyWeight": 0.18,
        "densityWeight": 0.3,
        "enduranceWeight": 0.12,
        "retentionWeight": 0.16,
        "energyWeight": 0.14,
        "compatibilityWeight": 0.1,
        "integrationPenalty": 0.24,
        "note": "capacity and bandwidth placement dominate"
      },
      {
        "id": "storage_scm_tier",
        "label": "Storage or SCM tier",
        "latencyWeight": 0.08,
        "densityWeight": 0.34,
        "enduranceWeight": 0.18,
        "retentionWeight": 0.24,
        "energyWeight": 0.08,
        "compatibilityWeight": 0.08,
        "integrationPenalty": 0.2,
        "note": "density, persistence, and endurance dominate"
      }
    ],
    "integration_contexts": [
      {
        "id": "logic_beol_embedded",
        "label": "Logic BEOL embedded",
        "riskBump": 0.18,
        "compatibilityNeed": 0.88,
        "thermalBump": 0.12,
        "maturityNeed": 0.72
      },
      {
        "id": "memory_array_standalone",
        "label": "Standalone memory array",
        "riskBump": 0.1,
        "compatibilityNeed": 0.62,
        "thermalBump": 0.18,
        "maturityNeed": 0.82
      },
      {
        "id": "3d_package_stack",
        "label": "3D package stack",
        "riskBump": 0.28,
        "compatibilityNeed": 0.7,
        "thermalBump": 0.34,
        "maturityNeed": 0.74
      },
      {
        "id": "ai_accelerator_tile",
        "label": "AI accelerator tile",
        "riskBump": 0.24,
        "compatibilityNeed": 0.76,
        "thermalBump": 0.28,
        "maturityNeed": 0.64
      }
    ],
    "workload_contexts": [
      {
        "id": "read_mostly_weights",
        "label": "Read-mostly weights",
        "enduranceStress": 0.18,
        "retentionStress": 0.22,
        "energyStress": 0.24,
        "latencyStress": 0.3,
        "accuracyStress": 0.36
      },
      {
        "id": "write_heavy_logging",
        "label": "Write-heavy logging",
        "enduranceStress": 0.62,
        "retentionStress": 0.26,
        "energyStress": 0.48,
        "latencyStress": 0.26,
        "accuracyStress": 0.2
      },
      {
        "id": "always_on_edge",
        "label": "Always-on edge",
        "enduranceStress": 0.28,
        "retentionStress": 0.48,
        "energyStress": 0.62,
        "latencyStress": 0.28,
        "accuracyStress": 0.28
      }
    ],
    "decision_priorities": [
      {
        "id": "latency_first",
        "label": "Latency-first",
        "latencyTilt": 0.18,
        "densityTilt": -0.04,
        "enduranceTilt": 0,
        "retentionTilt": -0.02,
        "energyTilt": 0.04
      },
      {
        "id": "density_cost_first",
        "label": "Density/cost-first",
        "latencyTilt": -0.06,
        "densityTilt": 0.18,
        "enduranceTilt": -0.02,
        "retentionTilt": 0.04,
        "energyTilt": 0
      },
      {
        "id": "reliability_first",
        "label": "Reliability-first",
        "latencyTilt": -0.02,
        "densityTilt": -0.02,
        "enduranceTilt": 0.14,
        "retentionTilt": 0.14,
        "energyTilt": -0.02
      }
    ]
  },
  "decision_gate_counts": {
    "retention_review": 172,
    "bounded_study_candidate": 129,
    "thermal_process_review": 328,
    "integration_risk_review": 972,
    "endurance_review": 88,
    "poor_fit_for_target": 39
  },
  "shortlist_examples": [],
  "high_risk_examples": [
    {
      "case_id": "sram_cache__near_logic_cache__3d_package_stack__write_heavy_logging__latency_first",
      "memory_label": "SRAM cache",
      "placement_target": "near_logic_cache",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__near_logic_cache__3d_package_stack__write_heavy_logging__density_cost_first",
      "memory_label": "SRAM cache",
      "placement_target": "near_logic_cache",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__near_logic_cache__3d_package_stack__write_heavy_logging__reliability_first",
      "memory_label": "SRAM cache",
      "placement_target": "near_logic_cache",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__near_logic_cache__3d_package_stack__always_on_edge__latency_first",
      "memory_label": "SRAM cache",
      "placement_target": "near_logic_cache",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__near_logic_cache__3d_package_stack__always_on_edge__density_cost_first",
      "memory_label": "SRAM cache",
      "placement_target": "near_logic_cache",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__near_logic_cache__3d_package_stack__always_on_edge__reliability_first",
      "memory_label": "SRAM cache",
      "placement_target": "near_logic_cache",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__embedded_code_config__3d_package_stack__write_heavy_logging__latency_first",
      "memory_label": "SRAM cache",
      "placement_target": "embedded_code_config",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__embedded_code_config__3d_package_stack__write_heavy_logging__density_cost_first",
      "memory_label": "SRAM cache",
      "placement_target": "embedded_code_config",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__embedded_code_config__3d_package_stack__write_heavy_logging__reliability_first",
      "memory_label": "SRAM cache",
      "placement_target": "embedded_code_config",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__embedded_code_config__3d_package_stack__always_on_edge__latency_first",
      "memory_label": "SRAM cache",
      "placement_target": "embedded_code_config",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__embedded_code_config__3d_package_stack__always_on_edge__density_cost_first",
      "memory_label": "SRAM cache",
      "placement_target": "embedded_code_config",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__embedded_code_config__3d_package_stack__always_on_edge__reliability_first",
      "memory_label": "SRAM cache",
      "placement_target": "embedded_code_config",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__main_near_memory__3d_package_stack__write_heavy_logging__latency_first",
      "memory_label": "SRAM cache",
      "placement_target": "main_near_memory",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__main_near_memory__3d_package_stack__write_heavy_logging__density_cost_first",
      "memory_label": "SRAM cache",
      "placement_target": "main_near_memory",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__main_near_memory__3d_package_stack__write_heavy_logging__reliability_first",
      "memory_label": "SRAM cache",
      "placement_target": "main_near_memory",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__main_near_memory__3d_package_stack__always_on_edge__latency_first",
      "memory_label": "SRAM cache",
      "placement_target": "main_near_memory",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__main_near_memory__3d_package_stack__always_on_edge__density_cost_first",
      "memory_label": "SRAM cache",
      "placement_target": "main_near_memory",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    },
    {
      "case_id": "sram_cache__main_near_memory__3d_package_stack__always_on_edge__reliability_first",
      "memory_label": "SRAM cache",
      "placement_target": "main_near_memory",
      "integration_context": "3d_package_stack",
      "decision_gate": "retention_review",
      "next_safe_check": "check retention distribution, bake/read conditions, and data-remanence boundary"
    }
  ],
  "role_views": [
    {
      "role": "device engineer",
      "reads": [
        "process_compatibility_score",
        "read_margin_risk",
        "integration_risk"
      ],
      "question": "Which device mechanism blocks the placement: variability, endurance, retention, or process compatibility?"
    },
    {
      "role": "memory architect",
      "reads": [
        "latency_fit_score",
        "density_fit_score",
        "placement_fit_score"
      ],
      "question": "Does this memory belong near logic, in a main-memory tier, in storage/SCM, or only as a bounded research candidate?"
    },
    {
      "role": "process integration",
      "reads": [
        "thermal_process_risk",
        "integration_risk",
        "process_compatibility_score"
      ],
      "question": "What module or package evidence would be needed before the cell-level promise can survive integration?"
    },
    {
      "role": "reliability/yield",
      "reads": [
        "endurance_fit_score",
        "retention_fit_score",
        "evidence_maturity_score"
      ],
      "question": "Which cycling, retention, read-margin, ECC, thermal, or qualification evidence is missing?"
    }
  ],
  "public_boundary": [
    "No live memory simulator, TCAD, SPICE, Ramulator, DRAMsim, compact-model calibration, or server-side solver is active.",
    "No vendor product ranking, benchmark table, memory-stack recommendation, foundry qualification, or reliability signoff is claimed.",
    "No paid article body, publisher figure, textbook table, course slide, code body, COMSOL file, PDK/model deck, standard-cell file, or proprietary memory data is copied.",
    "Rows are synthetic teaching proxies and require owned measured data before engineering reuse."
  ]
}