# GitHub Open-Source Seed Simulation Model Card

Generated from `GITHUB_OPEN_SOURCE_SEED_SWEEP_2026-08-14`.

These pages use original SemiAgora precomputed educational surrogate data. They
do not execute or copy third-party solver code, do not include PDK/model decks,
and do not expose process recipes, equipment-operation instructions, signoff
workflows, uploads, accounts, payments, comments, newsletter signup, or job/event
submission flows.

## Solver References

- Ramulator2 and DRAMsim3 are strong DRAM/HBM local-build candidates.
- DEVSIM remains the strongest open device/TCAD upgrade candidate.
- OpenRAM can be used later only through public PDK/toolchain boundaries.
- NeuroSim, MNSIM, CrossSim, CACTI, DESTINY, NVSim, PySpice, Xyce, Magic,
  Netgen, and Verilator remain link-only or manual-review unless license and
  dependency boundaries are explicitly cleared.

## Public Claim Boundary

These simulations are useful for concept learning, route design, UI rehearsal,
methods notes, and source-linked study. They are not calibrated engineering
signoff, measured silicon, qualified process data, memory-controller research
results, equipment instructions, or product-release evidence.