# HBM/base-die partition map model card

Version: 2026-08-21-v81

Experiment: SA-MEM-HBM-002

Execution mode: precomputed browser CSV replay only.

## Purpose

This artifact teaches how DRAM/HBM hierarchy decisions change when a base die may carry more controller, PHY, RAS telemetry, or custom die-to-die interface responsibility. The replay keeps bandwidth, capacity, thermal headroom, interposer/shoreline pressure, TSV PHY complexity, integration risk, and yield risk visible in one table.

## Data

- Rows: 1296
- Workload profiles: 4
- Partition strategies: 4
- Stack classes: 3
- Thermal classes: 3
- Interposer budgets: 3
- Yield postures: 3
- Live server runs: 0

## Source Boundary

The source spine is public link metadata and original SemiAgora interpretation only. It does not copy vendor NDA material, paid datasets, paper body text, JEDEC timing tables, controller IP, package design files, thermal solver output, or measured product data.

## Public Non-Claims

This dataset is not a product ranking, bandwidth certification, capacity guarantee, timing signoff, package qualification, thermal qualification, yield prediction, controller implementation guide, or live fab/APC control surface.

## Replacement Slots

Replace proxy fields with rights-cleared measured or licensed evidence only when available: workload traces, controller telemetry, bank/PHY counters, stack configuration, thermal simulation, interposer routing analysis, KGD/yield assumptions, and test coverage.