{ "schema": "semiagora.hbm-base-die-partition-map.v1", "version": "2026-08-21-v81", "execution_mode": "precomputed_browser_csv_replay_only", "source_run": { "run_id": "20260821_v81_manual_hbm_base_die_source_review", "evidence_path": "07_assets/memory_lab/experiments/SA-MEM-HBM-002/", "rights_mode": "public source links plus original SemiAgora synthetic teaching rows; no vendor NDA, paid data, copied paper body, stack design, controller IP, package database, or timing signoff material" }, "counts": { "rows": 1296, "workload_profiles": 4, "partition_strategies": 4, "stack_classes": 3, "thermal_classes": 3, "interposer_budgets": 3, "yield_postures": 3, "liveServerRuns": 0 }, "summary": { "decision_gate_counts": { "baseline_reading": 482, "yield_review": 216, "integration_review": 597, "partition_candidate": 1 }, "strategy_averages": [ { "partition_strategy": "standard_host_controller", "rows": 324, "mean_partition_score": "0.444", "mean_usable_bandwidth_index": "1.502", "mean_thermal_headroom_score": "0.786", "mean_yield_risk_proxy": "0.354", "mean_integration_risk_proxy": "0.445" }, { "partition_strategy": "controller_in_base_die", "rows": 324, "mean_partition_score": "0.510", "mean_usable_bandwidth_index": "1.679", "mean_thermal_headroom_score": "0.754", "mean_yield_risk_proxy": "0.404", "mean_integration_risk_proxy": "0.638" }, { "partition_strategy": "controller_phy_ras_in_base", "rows": 324, "mean_partition_score": "0.523", "mean_usable_bandwidth_index": "1.794", "mean_thermal_headroom_score": "0.731", "mean_yield_risk_proxy": "0.454", "mean_integration_risk_proxy": "0.853" }, { "partition_strategy": "custom_die_to_die_wrapper", "rows": 324, "mean_partition_score": "0.518", "mean_usable_bandwidth_index": "1.842", "mean_thermal_headroom_score": "0.715", "mean_yield_risk_proxy": "0.514", "mean_integration_risk_proxy": "0.920" } ], "top_partition_candidates": [ { "case_id": "HBM002-0445", "workload_profile": "llm_inference_kv_cache", "workload_note": "capacity pressure with repeated reads; controller locality can reduce host-side traffic", "partition_strategy": "controller_in_base_die", "partition_note": "moves scheduling and memory-control evidence closer to TSV/bank resources", "stack_class": "12hi_bandwidth_capacity", "stack_dies": 12, "interface_bits_proxy": 2048, "channels_proxy": 32, "thermal_class": "enhanced_lid", "interposer_budget": "balanced_interposer", "yield_posture": "conservative_kgd", "base_die_area_proxy": "0.380", "host_beachfront_relief_score": "0.368", "tsv_phy_complexity_score": "0.690", "controller_locality_score": "0.628", "interface_efficiency_score": "0.829", "usable_bandwidth_index": "2.270", "capacity_index": "1.032", "energy_per_bit_proxy": "1.376", "thermal_headroom_score": "0.710", "yield_risk_proxy": "0.269", "integration_risk_proxy": "0.657", "partition_score": "0.591", "decision_gate": "partition_candidate", "evidence_state": "proxy_candidate_requires_package_and_controller_review", "next_safe_check": "compare_against_host_controller_baseline_with_same_workload" } ], "most_thermal_constrained_rows": [] }, "role_views": [ { "role": "operator", "reads": [ "thermal_class", "thermal_headroom_score", "decision_gate", "next_safe_check" ], "use": "Keep thermal and package-state caution visible; do not turn the table into an operation or qualification workflow." }, { "role": "engineer", "reads": [ "partition_strategy", "controller_locality_score", "usable_bandwidth_index", "energy_per_bit_proxy" ], "use": "Compare controller/PHY/base-die placement against a host-controller baseline before naming a partition candidate." }, { "role": "integration", "reads": [ "interposer_budget", "host_beachfront_relief_score", "tsv_phy_complexity_score", "integration_risk_proxy" ], "use": "Check whether shoreline, interposer, TSV PHY, and package routing assumptions carry the selected partition." }, { "role": "yield", "reads": [ "stack_class", "yield_posture", "capacity_index", "yield_risk_proxy" ], "use": "Separate capacity gain from stack-yield and known-good-die review before reusing a claim." } ], "methods": [ "Cartesian sweep across workload, partition strategy, stack class, thermal class, interposer budget, and yield posture.", "Normalized proxy equations convert public vocabulary into bandwidth, capacity, thermal, yield, integration, and partition scores.", "Decision gates prioritize thermal, yield, and integration review before naming any base-die partition candidate.", "Rows are synthetic teaching data generated by SemiAgora; all measured replacements must be attached under the experiment folder before stronger claims are made." ], "public_boundary": [ "No vendor HBM stack, base-die floorplan, interposer database, TSV map, PHY macro, controller IP, JEDEC timing table, package CFD result, procurement data, or measured product data is included.", "No live architecture simulator, memory controller test, package thermal solver, SPICE solver, workload upload, account, payment, comment, newsletter signup, job/event submission, or qualification workflow is active.", "This page does not claim product release readiness, timing signoff, bandwidth certification, capacity guarantee, thermal qualification, yield prediction, or fab/APC control." ], "limitations": [ "The bandwidth, energy, thermal, yield, and integration values are normalized proxy scores, not calibrated HBM3e/HBM4 vendor specifications.", "The base-die partition strategies teach tradeoff shape only; they are not an implementation guide for a controller, PHY, RAS block, or die-to-die interface.", "The stack classes use generic 8-Hi, 12-Hi, and 16-Hi labels as teaching buckets and do not identify a real supplier stack.", "Real decisions require package design data, thermal simulation, controller verification, memory vendor constraints, test coverage, cost, and yield evidence not present here." ], "sources": [ { "label": "Micron HBM overview", "url": "https://www.micron.com/products/memory/hbm", "note": "Public HBM stack, base-die, TSV, microbump, interposer, channel, and wide-interface vocabulary anchor." }, { "label": "Semiconductor Engineering custom HBM", "url": "https://semiengineering.com/how-will-the-custom-hbm-business-work/", "note": "Public explanation of HBM4 custom base-die partitioning, host/controller placement, TSV PHY, RAS telemetry, and manufacturing/test responsibilities." }, { "label": "Marvell custom HBM overview", "url": "https://www.marvell.com/blogs/custom-hbm-what-is-it-and-why-its-the-future.html", "note": "Public custom-HBM base-die and interface discussion used only as a vocabulary source, not as a performance calibration." }, { "label": "Siemens HBM3e/HBM4 design guide", "url": "https://blogs.sw.siemens.com/semiconductor-packaging/2026/04/24/hbm3e-hbm4-ic-design-guide/", "note": "Public packaging/design context for HBM channel scaling, TSVs, interposer routing, PHY/controller changes, and thermal design pressure." }, { "label": "Synopsys HBM4/4E Controller IP", "url": "https://www.synopsys.com/designware-ip/interface-ip/hbm/hbm4-controller.html", "note": "Public controller/IP feature vocabulary for channels, pseudo channels, banks, RAS, refresh, QoS, ECC/CRC, PHY management, and custom HBM partition language." } ] }