# Layout RC Delay Evidence Ladder Model Card

Version: 2026-08-21-v79

## Purpose

This browser lab teaches how layout geometry becomes an RC proxy, then a delay, slew, and slack-risk proxy before a public timing claim is written. It is a report-literacy and evidence-order lab, not a live EDA flow.

## Dataset

- Rows: 3072
- Design contexts: inverter_chain, sram_wordline_driver_proxy, sram_bitline_sense_proxy, counter_clock_spine
- Topologies: short_local, cell_row, macro_edge, detoured_channel
- Layer classes: local_m1_like, intermediate_m2_m3_like, upper_m4_like
- Route styles: minimum_width, widened, shielded_neighbor, congestion_detour
- Load classes: fo1_logic, fo4_logic, sram_peripheral, clock_or_reset_fanout
- Checkpoints: schematic_load_only, floorplan_hpwl_proxy, global_route_estimate, pex_timing_proxy

## Public Boundary

- No PDK file, rule deck, Liberty, SPEF, SDC, GDS, DEF, extracted netlist, tool report, or OpenROAD/OpenLane project is redistributed.
- No live OpenROAD, OpenLane, OpenSTA, Magic, Netgen, ngspice, SPICE, TCAD, or server-side compiler runs.
- No timing closure, signoff, tapeout readiness, macro timing, SRAM compiler, foundry, yield, product, or qualification claim.

## Source Anchors

- OpenROAD documentation: https://openroad.readthedocs.io/en/latest/
- OpenROAD Flow Scripts: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts
- OpenLane 2 documentation: https://openlane2.readthedocs.io/en/latest/
- OpenSTA repository: https://github.com/The-OpenROAD-Project/OpenSTA
- SkyWater SKY130 PDK documentation: https://skywater-pdk.readthedocs.io/en/main/
- Magic VLSI: https://opencircuitdesign.com/magic/
- Netgen: https://opencircuitdesign.com/netgen/