{ "schema": "semiagora.m3d-igo-sram-integration-cell-subarray-evidence-ladder.v1", "version": "2026-08-27-v103", "experiment_id": "SA-MEM-M3D-IGO-SRAM-004", "title": "Monolithic-3D Si/oxide-semiconductor SRAM integration evidence ladder", "summary": "A deterministic browser packet connecting declared tier assignment, access transport, contact burden, inter-tier connection, WL/BL loading, thermal-budget compatibility, extraction maturity, cell/subarray sensitivities, contradictions, and owned replacement-evidence gates.", "execution_mode": "precomputed_browser_csv_replay_only", "counts": { "rows": 6144, "tier_assignment_states": 4, "access_transport_states": 4, "contact_burden_states": 4, "intertier_connection_states": 4, "wl_bl_loading_states": 3, "thermal_budget_states": 2, "extraction_maturity_states": 2, "evidence_posture_states": 2, "taxonomy_nodes_covered": 9, "source_anchors": 11, "copied_topology_rows": 0, "external_numeric_results": 0, "physical_dimensions": 0, "real_pdk_files": 0, "calibrated_models": 0, "live_tcad_runs": 0, "live_pex_runs": 0, "measured_silicon_rows": 0, "node_performance_claims": 0, "architecture_rankings": 0, "product_comparisons": 0, "signoff_actions": 0, "fabrication_recipe_actions": 0, "liveServerRuns": 0 }, "axes": { "tier_assignment_states": [ { "id": "single_tier_mathematical_reference", "label": "Single-tier mathematical reference", "verticalNeed": 0, "footprintFactor": 1, "balanceTarget": 0.82, "thermalSensitivity": 0.08, "evidenceScore": 60, "activeBeolTier": 0, "note": "Original single-tier reference only; it is not a copied SRAM topology or layout." }, { "id": "access_tier_separation_hypothesis", "label": "Access-tier separation hypothesis", "verticalNeed": 0.65, "footprintFactor": 0.78, "balanceTarget": 0.76, "thermalSensitivity": 0.35, "evidenceScore": 45, "activeBeolTier": 1, "note": "Original tier-separation abstraction with no device placement, layer, dimension, or route copied from a source." }, { "id": "load_access_tier_split_hypothesis", "label": "Load/access tier-split hypothesis", "verticalNeed": 0.82, "footprintFactor": 0.68, "balanceTarget": 0.7, "thermalSensitivity": 0.5, "evidenceScore": 35, "activeBeolTier": 1, "note": "Original high-partition teaching state; it is not a circuit diagram, netlist, or process stack." }, { "id": "maximal_vertical_partition_hypothesis", "label": "Maximal vertical-partition hypothesis", "verticalNeed": 1, "footprintFactor": 0.56, "balanceTarget": 0.64, "thermalSensitivity": 0.68, "evidenceScore": 25, "activeBeolTier": 1, "note": "Original boundary state used to expose evidence pressure, not an architecture recommendation." } ], "access_transport_states": [ { "id": "silicon_access_mathematical_reference", "label": "Silicon-access mathematical reference", "driveFactor": 1, "variabilityBurden": 0.1, "interfaceBurden": 0.15, "evidenceScore": 60, "note": "Dimensionless reference only; no silicon device value or compact-model parameter is used." }, { "id": "oxide_access_balanced_proxy", "label": "Oxide-access balanced proxy", "driveFactor": 0.82, "variabilityBurden": 0.18, "interfaceBurden": 0.3, "evidenceScore": 48, "note": "Original oxide-semiconductor sensitivity class, not an IGO or IGZO performance claim." }, { "id": "oxide_access_low_drive_proxy", "label": "Oxide-access low-drive proxy", "driveFactor": 0.64, "variabilityBurden": 0.24, "interfaceBurden": 0.42, "evidenceScore": 36, "note": "Original lower-drive teaching state with no reported mobility, current, geometry, or bias value." }, { "id": "unresolved_transport_replacement_gate", "label": "Unresolved transport replacement gate", "driveFactor": 0.72, "variabilityBurden": 0.35, "interfaceBurden": 0.55, "evidenceScore": 18, "note": "Names a missing model and measurement slot; it is not a device estimate." } ], "contact_burden_states": [ { "id": "ideal_contact_mathematical_reference", "label": "Ideal-contact mathematical reference", "transferFactor": 1, "seriesBurden": 0, "capacitanceBurden": 0.05, "evidenceScore": 10, "note": "Intentionally incomplete zero-series reference; never evidence that a real contact is ideal." }, { "id": "bounded_contact_proxy", "label": "Bounded-contact proxy", "transferFactor": 0.84, "seriesBurden": 0.16, "capacitanceBurden": 0.18, "evidenceScore": 45, "note": "Original contact sensitivity class without physical resistance, area, material, or extraction." }, { "id": "high_contact_burden_proxy", "label": "High-contact-burden proxy", "transferFactor": 0.62, "seriesBurden": 0.36, "capacitanceBurden": 0.34, "evidenceScore": 28, "note": "Original severe-burden state used to test contact/device contradiction handling." }, { "id": "unresolved_contact_replacement_gate", "label": "Unresolved contact replacement gate", "transferFactor": 0.55, "seriesBurden": 0.28, "capacitanceBurden": 0.4, "evidenceScore": 15, "note": "Names missing owned contact geometry, interface, extraction, variation, and uncertainty evidence." } ], "intertier_connection_states": [ { "id": "no_intertier_single_tier_reference", "label": "No-intertier single-tier reference", "continuityFactor": 1, "routingBurden": 0.08, "capacitanceBurden": 0.04, "evidenceScore": 55, "note": "Only consistent with the single-tier reference unless a contradiction is intentionally exposed." }, { "id": "conceptual_intertier_link", "label": "Conceptual inter-tier link", "continuityFactor": 0.58, "routingBurden": 0.28, "capacitanceBurden": 0.16, "evidenceScore": 18, "note": "Concept label only; no via, monolithic inter-tier connection, geometry, or parasitic is represented." }, { "id": "declared_local_intertier_proxy", "label": "Declared local inter-tier proxy", "continuityFactor": 0.82, "routingBurden": 0.48, "capacitanceBurden": 0.28, "evidenceScore": 45, "note": "Original local-link sensitivity state requiring owned connectivity and extraction evidence." }, { "id": "routing_heavy_intertier_proxy", "label": "Routing-heavy inter-tier proxy", "continuityFactor": 0.7, "routingBurden": 0.78, "capacitanceBurden": 0.46, "evidenceScore": 30, "note": "Original routing-pressure boundary, not a routed layout or PEX result." } ], "wl_bl_loading_states": [ { "id": "cell_local_loading_reference", "label": "Cell-local loading reference", "normalizedLoad": 0.35, "wordlineBurden": 0.25, "bitlineBurden": 0.3, "evidenceScore": 55, "note": "Mathematical local-load reference; it is not a physical cell capacitance or current." }, { "id": "compact_subarray_loading_proxy", "label": "Compact-subarray loading proxy", "normalizedLoad": 0.67, "wordlineBurden": 0.62, "bitlineBurden": 0.7, "evidenceScore": 42, "note": "Original subarray pressure class with no row count, column count, length, capacitance, or timing value." }, { "id": "routed_subarray_pressure_proxy", "label": "Routed-subarray pressure proxy", "normalizedLoad": 1, "wordlineBurden": 0.95, "bitlineBurden": 1, "evidenceScore": 28, "note": "Original upper loading boundary used to require owned WL/BL and periphery evidence." } ], "thermal_budget_states": [ { "id": "compatible_window_hypothesis", "label": "Compatible-window hypothesis", "compatibilityFactor": 0.88, "processStress": 0.15, "evidenceScore": 55, "note": "Declared compatibility hypothesis only; no temperature, time, material, diffusion, or process sequence is supplied." }, { "id": "constrained_window_hypothesis", "label": "Constrained-window hypothesis", "compatibilityFactor": 0.5, "processStress": 0.5, "evidenceScore": 25, "note": "Original constrained boundary that names the need for an owned thermal/process budget." } ], "extraction_maturity_states": [ { "id": "conceptual_no_extraction", "label": "Conceptual / no extraction", "confidenceFactor": 0.2, "coverageFactor": 0.15, "evidenceScore": 20, "note": "No RC extraction has been performed; all loading remains declared and dimensionless." }, { "id": "deterministic_proxy_envelope", "label": "Deterministic proxy envelope", "confidenceFactor": 0.64, "coverageFactor": 0.7, "evidenceScore": 50, "note": "Original deterministic envelope only; it is not rule-based extraction, PEX, a corner deck, or signoff." } ], "evidence_posture_states": [ { "id": "scoping_only_posture", "label": "Scoping-only posture", "confidenceFactor": 0.3, "reviewFactor": 0.25, "evidenceScore": 30, "note": "Vocabulary and model-boundary review only; no owned replacement packet is asserted." }, { "id": "replacement_plan_declared", "label": "Replacement plan declared", "confidenceFactor": 0.68, "reviewFactor": 0.7, "evidenceScore": 60, "note": "A plan for owned evidence is declared, but no measurement, model, extraction, or review result is included." } ] }, "methods": [ "Generate the complete 4 x 4 x 4 x 4 x 3 x 2 x 2 x 2 Cartesian sweep with no randomness, fitting, optimization, hidden state, source-result calibration, or external device value.", "Use original dimensionless access, contact, inter-tier, thermal, extraction, loading, stability, delay, energy, footprint, and evidence equations; none is a calibrated device, compact-model, circuit, layout, or process solver.", "Emit explicit contradictions when tier, transport, contact, inter-tier, loading, thermal, extraction, or evidence-posture declarations disagree, then route every row to the next owned-evidence gate.", "Keep nine topic-specific claim maps and eleven primary, official, roadmap, model-lineage, and metrology anchors separate from all generated coefficients and rows." ], "limitations": [ "No TCAD, compact-model fitting, SPICE, SRAM SNM extraction, transient simulation, virtual fabrication, layout, RC extraction, PEX, thermal, variation, Monte Carlo, or live server solver is executed.", "The scores are dimensionless within-packet sensitivities, not mobility, current, resistance, capacitance, SNM, write margin, delay, energy, leakage, area, yield, technology readiness, or signoff metrics.", "No topology, device stack, material, dimension, process window, node, foundry, architecture, product, or performance result is predicted, selected, ranked, or qualified." ], "public_boundary": [ "Zero copied topology rows, external numeric results, physical dimensions, real PDK files, calibrated models, live TCAD/PEX runs, measured silicon rows, node claims, rankings, comparisons, signoff actions, recipes, or live server runs enter the dataset.", "No source-reported topology, layout, parameter, extraction, percentage, node claim, figure, table, equation, result, or conclusion is converted into a model coefficient.", "No fabrication recipe, device/process recommendation, architecture winner, product comparison, foundry claim, tapeout readiness, qualification, or signoff action is provided.", "A real claim requires owned topology and condition cards, device/compact-model lineage, contacts, cross-tier connectivity, thermal budget, layout/PEX, cell and subarray simulation, variation, uncertainty, measured evidence, and accountable review." ], "source_observation": { "observation_date": "2026-08-27", "mode": "Primary, official, rights-holder, model-lineage, and metrology link review only.", "exclusion": "No source-reported numeric result, topology, geometry, process condition, equation, figure, table, model, extracted parasitic, comparison, or node claim is used as a model input." }, "sources": [ { "id": "src-arxiv-m3d-igo-sram-2608-22741", "label": "arXiv: process-aware hybrid Si/IGO monolithic-3D SRAM preprint record", "organization": "arXiv / research authors", "url": "https://arxiv.org/abs/2608.22741", "sourceClass": "primary-preprint-metadata", "rights": "Public metadata, abstract-level scope, version history, and link only; no paper body, topology, layout, dimension, equation, TCAD, extraction, result, percentage, or node claim is copied.", "note": "Scope anchor for the device-tier, integration, cell, and subarray evidence chain; it supplies zero numeric model inputs." }, { "id": "src-ieee-m3d-sram-beol-2023", "label": "IEEE: monolithic-3D SRAM with BEOL-compatible transistors", "organization": "IEEE / research authors", "url": "https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134152", "sourceClass": "primary-conference-metadata", "rights": "DOI metadata and abstract-level scope only; no controlled body, figure, table, circuit detail, value, or conclusion is mirrored.", "note": "BEOL-compatible transistor and SRAM integration vocabulary anchor without importing a design or result." }, { "id": "src-ieee-hybrid-igzo-si-sram-2024", "label": "IEEE: hybrid IGZO/Si SRAM monolithic-3D demonstration record", "organization": "IEEE / research authors", "url": "https://doi.org/10.1109/VLSITECHNOLOGYANDCIR46783.2024.10631551", "sourceClass": "primary-conference-metadata", "rights": "DOI metadata and abstract-level scope only; no device stack, process condition, topology, curve, value, figure, table, or comparison is copied.", "note": "Hybrid oxide-semiconductor/silicon integration evidence anchor with all reported values excluded." }, { "id": "src-ieee-m3d-sram-tft-2025", "label": "IEEE: monolithic-3D SRAMs using thin-film transistors", "organization": "IEEE / research authors", "url": "https://doi.org/10.1109/IEDM50572.2025.11353709", "sourceClass": "primary-conference-metadata", "rights": "DOI metadata and abstract-level opportunity/challenge scope only; no body, figure, table, dimension, value, roadmap claim, or ranking is copied.", "note": "Evidence-maturity and integration-challenge vocabulary anchor." }, { "id": "src-advscience-igzo-device-circuit-2025", "label": "Advanced Science / PMC: IGZO device-to-circuit co-design record", "organization": "Research authors / PubMed Central", "url": "https://pmc.ncbi.nlm.nih.gov/articles/PMC12866809/", "sourceClass": "open-primary-journal-link", "rights": "Open article link, metadata, and original synthesis only; no article text, figure, table, equation, process condition, device parameter, circuit result, or performance value is copied.", "note": "Device-to-circuit handoff vocabulary anchor; no coefficient is calibrated from the article." }, { "id": "src-imec-igzo-dram", "label": "imec: capacitor-less IGZO DRAM research summary", "organization": "imec", "url": "https://www.imec-int.com/en/press/imec-demonstrates-capacitor-less-igzo-based-dram-cell-400s-retention-time", "sourceClass": "rights-holder-research-summary", "rights": "Rights-holder link and original synthesis only; no image, reported retention value, process detail, device curve, product claim, or DRAM-to-SRAM transfer is copied.", "note": "Oxide-semiconductor memory and integration vocabulary anchor; DRAM results are not treated as SRAM evidence." }, { "id": "src-nist-emerging-integrated-systems", "label": "NIST: metrology for emerging integrated systems", "organization": "NIST", "url": "https://www.nist.gov/programs-projects/metrology-emerging-integrated-systems", "sourceClass": "government-metrology-program", "rights": "Official program link and original synthesis only; no procedure, requirement, controlled content, or program-compliance claim is copied.", "note": "Structure, interface, integration, and measurement-evidence vocabulary anchor." }, { "id": "src-nist-irds-metrology-2024", "label": "NIST / IRDS: 2024 Metrology chapter record", "organization": "NIST / IRDS", "url": "https://www.nist.gov/publications/international-roadmap-devices-and-systems-tm-2024-metrology", "sourceClass": "government-roadmap-metadata", "rights": "Official metadata and link only; no roadmap body, table, target, figure, requirement, or value is mirrored.", "note": "Measurement readiness, structure-function linkage, and uncertainty vocabulary anchor." }, { "id": "src-imec-logic-roadmap", "label": "imec: logic technology roadmap", "organization": "imec", "url": "https://www.imec-int.com/en/articles/view-logic-technology-roadmap", "sourceClass": "rights-holder-roadmap-summary", "rights": "Rights-holder link and original synthesis only; no roadmap figure, node target, process detail, PPA value, or foundry comparison is copied.", "note": "Staged integration and evidence-maturity vocabulary anchor without a node claim." }, { "id": "src-bsim-models", "label": "UC Berkeley: BSIM model index", "organization": "UC Berkeley BSIM Group", "url": "https://www.bsim.berkeley.edu/models/", "sourceClass": "official-model-documentation-index", "rights": "Official model-index link and original synthesis only; no model file, parameter, calibrated card, PDK, or oxide-semiconductor model claim is copied.", "note": "Compact-model lineage and model-boundary vocabulary anchor; no oxide-semiconductor model, parameter set, calibrated card, or device prediction is supplied." }, { "id": "src-nist-tn1297", "label": "NIST Technical Note 1297: measurement uncertainty", "organization": "NIST", "url": "https://www.nist.gov/pml/nist-technical-note-1297", "sourceClass": "government-metrology-guidance", "rights": "Official guidance link and original synthesis only; no controlled guidance text is mirrored or treated as a completed formal uncertainty budget.", "note": "Measurand, uncertainty, and reporting-lineage vocabulary anchor; no formal uncertainty budget is claimed." } ] }