{
  "schema": "semiagora.device-architecture-comparison.v1",
  "version": "2026-08-22-v91",
  "generated_date": "2026-08-22",
  "execution_mode": "precomputed_browser_csv_replay_only",
  "title": "MOSFET, FinFET, GAAFET, and CFET architecture comparison replay",
  "slug": "mosfet-finfet-gaafet-cfet-architecture-comparison-replay",
  "route": "/simulations/mosfet-finfet-gaafet-cfet-architecture-comparison-replay",
  "lesson_route": "/learn/mosfet-finfet-gaafet-cfet-architecture-comparison",
  "lab_route": "/labs/mosfet-finfet-gaafet-cfet-architecture-comparison",
  "experiment_id": "SA-DEV-GAAFET-COMPARISON-002",
  "description": "A rights-clean browser replay for comparing architecture context, electrostatic control, contact and capacitance burden, variability, thermal coupling, integration risk, evidence maturity, and circuit handoff without ranking nodes or products.",
  "counts": {
    "rows": 4096,
    "architectures": 4,
    "scaling_contexts": 4,
    "contact_strategies": 4,
    "variability_modes": 4,
    "circuit_contexts": 4,
    "review_postures": 4,
    "liveServerRuns": 0
  },
  "axes": {
    "architectures": [
      {
        "id": "planar_mosfet",
        "label": "Planar MOSFET",
        "control": 62,
        "drive": 52,
        "capacitance": 28,
        "contact": 24,
        "variability": 32,
        "thermal": 22,
        "integration": 20,
        "maturity": 90,
        "context": "single-plane gate and mature device-to-circuit handoff context"
      },
      {
        "id": "finfet",
        "label": "FinFET",
        "control": 72,
        "drive": 66,
        "capacitance": 38,
        "contact": 34,
        "variability": 38,
        "thermal": 30,
        "integration": 34,
        "maturity": 84,
        "context": "three-sided gate control with fin-count quantization and local-access pressure"
      },
      {
        "id": "gaa_nanosheet",
        "label": "GAAFET nanosheet",
        "control": 87,
        "drive": 80,
        "capacitance": 48,
        "contact": 46,
        "variability": 36,
        "thermal": 40,
        "integration": 50,
        "maturity": 70,
        "context": "gate-all-around control with sheet-width freedom, inner-spacer, and contact burden"
      },
      {
        "id": "cfet",
        "label": "CFET",
        "control": 84,
        "drive": 92,
        "capacitance": 60,
        "contact": 60,
        "variability": 52,
        "thermal": 62,
        "integration": 68,
        "maturity": 50,
        "context": "vertically stacked n/p device context where density, contacts, vias, heat, and overlay move together"
      }
    ],
    "scaling_contexts": [
      {
        "id": "relaxed_electrostatic_baseline",
        "label": "Relaxed electrostatic baseline",
        "control": 12,
        "drive": -6,
        "capacitance": -8,
        "contact": -4,
        "variability": -8,
        "thermal": -4,
        "integration": -8
      },
      {
        "id": "short_channel_pressure",
        "label": "Short-channel pressure",
        "control": -9,
        "drive": 8,
        "capacitance": 4,
        "contact": 3,
        "variability": 7,
        "thermal": 3,
        "integration": 5
      },
      {
        "id": "leakage_guarded_operation",
        "label": "Leakage-guarded operation",
        "control": -4,
        "drive": -2,
        "capacitance": 2,
        "contact": 2,
        "variability": 9,
        "thermal": 2,
        "integration": 4
      },
      {
        "id": "density_limited_cell",
        "label": "Density-limited cell",
        "control": 0,
        "drive": 10,
        "capacitance": 12,
        "contact": 14,
        "variability": 5,
        "thermal": 7,
        "integration": 11
      }
    ],
    "contact_strategies": [
      {
        "id": "conventional_frontside_mol",
        "label": "Conventional frontside MOL",
        "drive": -2,
        "capacitance": 7,
        "contact": 8,
        "thermal": 0,
        "integration": 0,
        "maturity": 8,
        "context": "frontside contact and local-interconnect baseline"
      },
      {
        "id": "self_aligned_local_contact",
        "label": "Self-aligned local contact",
        "drive": 4,
        "capacitance": 3,
        "contact": -7,
        "thermal": 1,
        "integration": 9,
        "maturity": 4,
        "context": "local contact benefit with alignment and integration review"
      },
      {
        "id": "backside_power_assisted",
        "label": "Backside-power-assisted handoff",
        "drive": 5,
        "capacitance": -3,
        "contact": -4,
        "thermal": 5,
        "integration": 19,
        "maturity": -3,
        "context": "power-delivery relief paired with backside integration evidence"
      },
      {
        "id": "vertically_stacked_contacts",
        "label": "Vertically stacked top/bottom contacts",
        "drive": 7,
        "capacitance": 15,
        "contact": 19,
        "thermal": 10,
        "integration": 25,
        "maturity": -12,
        "context": "CFET-specific top/bottom access and via-stack review"
      }
    ],
    "variability_modes": [
      {
        "id": "edge_cd_variation",
        "label": "Edge and CD variation",
        "control": -3,
        "drive": -2,
        "capacitance": 2,
        "contact": 1,
        "variability": 14,
        "thermal": 0,
        "integration": 3,
        "context": "pattern edge and critical-dimension sensitivity"
      },
      {
        "id": "geometry_quantization",
        "label": "Geometry quantization",
        "control": -2,
        "drive": -5,
        "capacitance": 3,
        "contact": 2,
        "variability": 18,
        "thermal": 0,
        "integration": 4,
        "context": "fin-count or sheet-geometry discretization sensitivity"
      },
      {
        "id": "workfunction_interface",
        "label": "Work-function and interface variation",
        "control": -5,
        "drive": -3,
        "capacitance": 1,
        "contact": 0,
        "variability": 20,
        "thermal": 1,
        "integration": 5,
        "context": "threshold, interface, and gate-stack sensitivity"
      },
      {
        "id": "vertical_overlay_alignment",
        "label": "Vertical overlay and alignment",
        "control": -2,
        "drive": -2,
        "capacitance": 7,
        "contact": 10,
        "variability": 24,
        "thermal": 4,
        "integration": 13,
        "context": "vertical alignment, stacked-access, and overlay sensitivity"
      }
    ],
    "circuit_contexts": [
      {
        "id": "inverter_chain",
        "label": "Inverter chain",
        "drive": 3,
        "capacitance": 2,
        "contact": 1,
        "variability": 1,
        "thermal": 0,
        "integration": 0,
        "readiness": 8,
        "context": "single-path delay and slew handoff"
      },
      {
        "id": "local_clock_buffer",
        "label": "Local clock buffer",
        "drive": 5,
        "capacitance": 11,
        "contact": 4,
        "variability": 4,
        "thermal": 4,
        "integration": 3,
        "readiness": 2,
        "context": "capacitance, slew, and switching-power sensitivity"
      },
      {
        "id": "sram_edge_peripheral",
        "label": "SRAM edge peripheral",
        "drive": 2,
        "capacitance": 6,
        "contact": 6,
        "variability": 10,
        "thermal": 3,
        "integration": 5,
        "readiness": 0,
        "context": "local routing, matching, and decision-margin sensitivity"
      },
      {
        "id": "dense_datapath_cell",
        "label": "Dense datapath cell",
        "drive": 6,
        "capacitance": 9,
        "contact": 9,
        "variability": 5,
        "thermal": 6,
        "integration": 8,
        "readiness": 1,
        "context": "footprint benefit checked against routing and parasitic burden"
      }
    ],
    "review_postures": [
      {
        "id": "architecture_vocabulary_only",
        "label": "Architecture vocabulary only",
        "evidence": 34,
        "readiness": -10,
        "check": "keep the row as vocabulary only and attach architecture-specific source evidence"
      },
      {
        "id": "normalized_teaching_proxy",
        "label": "Normalized teaching proxy",
        "evidence": 48,
        "readiness": -3,
        "check": "keep normalized units visible and block cross-node or product ranking"
      },
      {
        "id": "cross_domain_review_packet",
        "label": "Cross-domain review packet",
        "evidence": 63,
        "readiness": 5,
        "check": "review device, contact, interconnect, variability, thermal, and circuit owners together"
      },
      {
        "id": "replacement_evidence_plan",
        "label": "Replacement-evidence plan",
        "evidence": 74,
        "readiness": 9,
        "check": "replace proxies with owned calibrated models, extraction, metrology, and circuit data"
      }
    ]
  },
  "summary": {
    "decision_gate_counts": {
      "owner_review_required": 804,
      "bounded_teaching_case": 482,
      "bounded_comparison_case": 176,
      "architecture_context_review": 960,
      "electrostatic_control_review": 432,
      "device_to_circuit_review": 84,
      "variability_review": 520,
      "integration_review": 94,
      "parasitic_handoff_review": 328,
      "evidence_boundary_review": 192,
      "thermal_coupling_review": 24
    },
    "average_electrostatic_control_score": "70.56",
    "average_drive_per_footprint_proxy": "76.54",
    "average_capacitance_burden_proxy": "60.62",
    "average_contact_resistance_burden_proxy": "57.73",
    "average_variability_sensitivity_proxy": "70.42",
    "average_thermal_coupling_proxy": "47.25",
    "average_integration_risk_proxy": "71.56",
    "average_evidence_maturity_score": "60.04",
    "average_circuit_handoff_readiness_score": "57.08",
    "average_comparison_readiness_score": "54.15",
    "architecture_proxy_averages": [
      {
        "architecture": "planar_mosfet",
        "label": "Planar MOSFET",
        "rows": 1024,
        "average_electrostatic_control_score": "56.50",
        "average_contact_resistance_burden_proxy": "40.50",
        "average_variability_sensitivity_proxy": "61.50",
        "average_integration_risk_proxy": "50.50",
        "note": "Normalized averages for this synthetic sweep only; not a node, vendor, product, or architecture ranking."
      },
      {
        "architecture": "finfet",
        "label": "FinFET",
        "rows": 1024,
        "average_electrostatic_control_score": "66.50",
        "average_contact_resistance_burden_proxy": "50.50",
        "average_variability_sensitivity_proxy": "69.50",
        "average_integration_risk_proxy": "64.45",
        "note": "Normalized averages for this synthetic sweep only; not a node, vendor, product, or architecture ranking."
      },
      {
        "architecture": "gaa_nanosheet",
        "label": "GAAFET nanosheet",
        "rows": 1024,
        "average_electrostatic_control_score": "80.75",
        "average_contact_resistance_burden_proxy": "62.46",
        "average_variability_sensitivity_proxy": "67.00",
        "average_integration_risk_proxy": "78.98",
        "note": "Normalized averages for this synthetic sweep only; not a node, vendor, product, or architecture ranking."
      },
      {
        "architecture": "cfet",
        "label": "CFET",
        "rows": 1024,
        "average_electrostatic_control_score": "78.50",
        "average_contact_resistance_burden_proxy": "77.48",
        "average_variability_sensitivity_proxy": "83.70",
        "average_integration_risk_proxy": "92.31",
        "note": "Normalized averages for this synthetic sweep only; not a node, vendor, product, or architecture ranking."
      }
    ],
    "bounded_examples": [
      {
        "case_id": "ARCHCMP-0003",
        "architecture": "planar_mosfet",
        "architecture_label": "Planar MOSFET",
        "scaling_context": "relaxed_electrostatic_baseline",
        "scaling_context_label": "Relaxed electrostatic baseline",
        "contact_strategy": "conventional_frontside_mol",
        "contact_strategy_label": "Conventional frontside MOL",
        "variability_mode": "edge_cd_variation",
        "variability_mode_label": "Edge and CD variation",
        "circuit_context": "inverter_chain",
        "circuit_context_label": "Inverter chain",
        "review_posture": "cross_domain_review_packet",
        "review_posture_label": "Cross-domain review packet",
        "electrostatic_control_score": "68.75",
        "drive_per_footprint_proxy": "43.25",
        "capacitance_burden_proxy": "28.75",
        "contact_resistance_burden_proxy": "28.00",
        "variability_sensitivity_proxy": "41.25",
        "thermal_coupling_proxy": "16.25",
        "integration_risk_proxy": "15.00",
        "evidence_maturity_score": "79.17",
        "circuit_handoff_readiness_score": "75.08",
        "comparison_readiness_score": "76.15",
        "decision_gate": "bounded_comparison_case",
        "evidence_state": "bounded contextual comparison case",
        "next_safe_check": "use only as a contextual teaching comparison with all non-ranking limits attached",
        "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; single-path delay and slew handoff"
      },
      {
        "case_id": "ARCHCMP-0004",
        "architecture": "planar_mosfet",
        "architecture_label": "Planar MOSFET",
        "scaling_context": "relaxed_electrostatic_baseline",
        "scaling_context_label": "Relaxed electrostatic baseline",
        "contact_strategy": "conventional_frontside_mol",
        "contact_strategy_label": "Conventional frontside MOL",
        "variability_mode": "edge_cd_variation",
        "variability_mode_label": "Edge and CD variation",
        "circuit_context": "inverter_chain",
        "circuit_context_label": "Inverter chain",
        "review_posture": "replacement_evidence_plan",
        "review_posture_label": "Replacement-evidence plan",
        "electrostatic_control_score": "68.75",
        "drive_per_footprint_proxy": "43.25",
        "capacitance_burden_proxy": "28.75",
        "contact_resistance_burden_proxy": "28.00",
        "variability_sensitivity_proxy": "41.25",
        "thermal_coupling_proxy": "16.25",
        "integration_risk_proxy": "15.00",
        "evidence_maturity_score": "85.44",
        "circuit_handoff_readiness_score": "75.58",
        "comparison_readiness_score": "81.33",
        "decision_gate": "bounded_comparison_case",
        "evidence_state": "bounded contextual comparison case",
        "next_safe_check": "use only as a contextual teaching comparison with all non-ranking limits attached",
        "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; single-path delay and slew handoff"
      },
      {
        "case_id": "ARCHCMP-0007",
        "architecture": "planar_mosfet",
        "architecture_label": "Planar MOSFET",
        "scaling_context": "relaxed_electrostatic_baseline",
        "scaling_context_label": "Relaxed electrostatic baseline",
        "contact_strategy": "conventional_frontside_mol",
        "contact_strategy_label": "Conventional frontside MOL",
        "variability_mode": "edge_cd_variation",
        "variability_mode_label": "Edge and CD variation",
        "circuit_context": "local_clock_buffer",
        "circuit_context_label": "Local clock buffer",
        "review_posture": "cross_domain_review_packet",
        "review_posture_label": "Cross-domain review packet",
        "electrostatic_control_score": "68.75",
        "drive_per_footprint_proxy": "45.25",
        "capacitance_burden_proxy": "37.75",
        "contact_resistance_burden_proxy": "31.00",
        "variability_sensitivity_proxy": "44.25",
        "thermal_coupling_proxy": "20.25",
        "integration_risk_proxy": "18.00",
        "evidence_maturity_score": "79.17",
        "circuit_handoff_readiness_score": "67.05",
        "comparison_readiness_score": "72.76",
        "decision_gate": "bounded_comparison_case",
        "evidence_state": "bounded contextual comparison case",
        "next_safe_check": "use only as a contextual teaching comparison with all non-ranking limits attached",
        "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; capacitance, slew, and switching-power sensitivity"
      },
      {
        "case_id": "ARCHCMP-0008",
        "architecture": "planar_mosfet",
        "architecture_label": "Planar MOSFET",
        "scaling_context": "relaxed_electrostatic_baseline",
        "scaling_context_label": "Relaxed electrostatic baseline",
        "contact_strategy": "conventional_frontside_mol",
        "contact_strategy_label": "Conventional frontside MOL",
        "variability_mode": "edge_cd_variation",
        "variability_mode_label": "Edge and CD variation",
        "circuit_context": "local_clock_buffer",
        "circuit_context_label": "Local clock buffer",
        "review_posture": "replacement_evidence_plan",
        "review_posture_label": "Replacement-evidence plan",
        "electrostatic_control_score": "68.75",
        "drive_per_footprint_proxy": "45.25",
        "capacitance_burden_proxy": "37.75",
        "contact_resistance_burden_proxy": "31.00",
        "variability_sensitivity_proxy": "44.25",
        "thermal_coupling_proxy": "20.25",
        "integration_risk_proxy": "18.00",
        "evidence_maturity_score": "85.44",
        "circuit_handoff_readiness_score": "67.55",
        "comparison_readiness_score": "77.94",
        "decision_gate": "bounded_comparison_case",
        "evidence_state": "bounded contextual comparison case",
        "next_safe_check": "use only as a contextual teaching comparison with all non-ranking limits attached",
        "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; capacitance, slew, and switching-power sensitivity"
      },
      {
        "case_id": "ARCHCMP-0012",
        "architecture": "planar_mosfet",
        "architecture_label": "Planar MOSFET",
        "scaling_context": "relaxed_electrostatic_baseline",
        "scaling_context_label": "Relaxed electrostatic baseline",
        "contact_strategy": "conventional_frontside_mol",
        "contact_strategy_label": "Conventional frontside MOL",
        "variability_mode": "edge_cd_variation",
        "variability_mode_label": "Edge and CD variation",
        "circuit_context": "sram_edge_peripheral",
        "circuit_context_label": "SRAM edge peripheral",
        "review_posture": "replacement_evidence_plan",
        "review_posture_label": "Replacement-evidence plan",
        "electrostatic_control_score": "68.75",
        "drive_per_footprint_proxy": "42.25",
        "capacitance_burden_proxy": "32.75",
        "contact_resistance_burden_proxy": "33.00",
        "variability_sensitivity_proxy": "50.25",
        "thermal_coupling_proxy": "19.25",
        "integration_risk_proxy": "20.00",
        "evidence_maturity_score": "85.44",
        "circuit_handoff_readiness_score": "64.70",
        "comparison_readiness_score": "76.72",
        "decision_gate": "bounded_comparison_case",
        "evidence_state": "bounded contextual comparison case",
        "next_safe_check": "use only as a contextual teaching comparison with all non-ranking limits attached",
        "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; local routing, matching, and decision-margin sensitivity"
      },
      {
        "case_id": "ARCHCMP-0016",
        "architecture": "planar_mosfet",
        "architecture_label": "Planar MOSFET",
        "scaling_context": "relaxed_electrostatic_baseline",
        "scaling_context_label": "Relaxed electrostatic baseline",
        "contact_strategy": "conventional_frontside_mol",
        "contact_strategy_label": "Conventional frontside MOL",
        "variability_mode": "edge_cd_variation",
        "variability_mode_label": "Edge and CD variation",
        "circuit_context": "dense_datapath_cell",
        "circuit_context_label": "Dense datapath cell",
        "review_posture": "replacement_evidence_plan",
        "review_posture_label": "Replacement-evidence plan",
        "electrostatic_control_score": "68.75",
        "drive_per_footprint_proxy": "46.25",
        "capacitance_burden_proxy": "35.75",
        "contact_resistance_burden_proxy": "36.00",
        "variability_sensitivity_proxy": "45.25",
        "thermal_coupling_proxy": "22.25",
        "integration_risk_proxy": "23.00",
        "evidence_maturity_score": "85.44",
        "circuit_handoff_readiness_score": "65.77",
        "comparison_readiness_score": "76.86",
        "decision_gate": "bounded_comparison_case",
        "evidence_state": "bounded contextual comparison case",
        "next_safe_check": "use only as a contextual teaching comparison with all non-ranking limits attached",
        "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; footprint benefit checked against routing and parasitic burden"
      },
      {
        "case_id": "ARCHCMP-0019",
        "architecture": "planar_mosfet",
        "architecture_label": "Planar MOSFET",
        "scaling_context": "relaxed_electrostatic_baseline",
        "scaling_context_label": "Relaxed electrostatic baseline",
        "contact_strategy": "conventional_frontside_mol",
        "contact_strategy_label": "Conventional frontside MOL",
        "variability_mode": "geometry_quantization",
        "variability_mode_label": "Geometry quantization",
        "circuit_context": "inverter_chain",
        "circuit_context_label": "Inverter chain",
        "review_posture": "cross_domain_review_packet",
        "review_posture_label": "Cross-domain review packet",
        "electrostatic_control_score": "69.75",
        "drive_per_footprint_proxy": "40.25",
        "capacitance_burden_proxy": "29.75",
        "contact_resistance_burden_proxy": "29.00",
        "variability_sensitivity_proxy": "45.25",
        "thermal_coupling_proxy": "16.25",
        "integration_risk_proxy": "16.00",
        "evidence_maturity_score": "79.17",
        "circuit_handoff_readiness_score": "74.01",
        "comparison_readiness_score": "75.16",
        "decision_gate": "bounded_comparison_case",
        "evidence_state": "bounded contextual comparison case",
        "next_safe_check": "use only as a contextual teaching comparison with all non-ranking limits attached",
        "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; fin-count or sheet-geometry discretization sensitivity; single-path delay and slew handoff"
      },
      {
        "case_id": "ARCHCMP-0020",
        "architecture": "planar_mosfet",
        "architecture_label": "Planar MOSFET",
        "scaling_context": "relaxed_electrostatic_baseline",
        "scaling_context_label": "Relaxed electrostatic baseline",
        "contact_strategy": "conventional_frontside_mol",
        "contact_strategy_label": "Conventional frontside MOL",
        "variability_mode": "geometry_quantization",
        "variability_mode_label": "Geometry quantization",
        "circuit_context": "inverter_chain",
        "circuit_context_label": "Inverter chain",
        "review_posture": "replacement_evidence_plan",
        "review_posture_label": "Replacement-evidence plan",
        "electrostatic_control_score": "69.75",
        "drive_per_footprint_proxy": "40.25",
        "capacitance_burden_proxy": "29.75",
        "contact_resistance_burden_proxy": "29.00",
        "variability_sensitivity_proxy": "45.25",
        "thermal_coupling_proxy": "16.25",
        "integration_risk_proxy": "16.00",
        "evidence_maturity_score": "85.44",
        "circuit_handoff_readiness_score": "74.51",
        "comparison_readiness_score": "80.34",
        "decision_gate": "bounded_comparison_case",
        "evidence_state": "bounded contextual comparison case",
        "next_safe_check": "use only as a contextual teaching comparison with all non-ranking limits attached",
        "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; fin-count or sheet-geometry discretization sensitivity; single-path delay and slew handoff"
      }
    ]
  },
  "example_rows": [
    {
      "case_id": "ARCHCMP-0001",
      "architecture": "planar_mosfet",
      "architecture_label": "Planar MOSFET",
      "scaling_context": "relaxed_electrostatic_baseline",
      "scaling_context_label": "Relaxed electrostatic baseline",
      "contact_strategy": "conventional_frontside_mol",
      "contact_strategy_label": "Conventional frontside MOL",
      "variability_mode": "edge_cd_variation",
      "variability_mode_label": "Edge and CD variation",
      "circuit_context": "inverter_chain",
      "circuit_context_label": "Inverter chain",
      "review_posture": "architecture_vocabulary_only",
      "review_posture_label": "Architecture vocabulary only",
      "electrostatic_control_score": "68.75",
      "drive_per_footprint_proxy": "43.25",
      "capacitance_burden_proxy": "28.75",
      "contact_resistance_burden_proxy": "28.00",
      "variability_sensitivity_proxy": "41.25",
      "thermal_coupling_proxy": "16.25",
      "integration_risk_proxy": "15.00",
      "evidence_maturity_score": "62.64",
      "circuit_handoff_readiness_score": "73.75",
      "comparison_readiness_score": "58.03",
      "decision_gate": "owner_review_required",
      "evidence_state": "cross-domain owner review required",
      "next_safe_check": "route to device, integration, extraction, and circuit owners before any architecture claim",
      "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; single-path delay and slew handoff"
    },
    {
      "case_id": "ARCHCMP-0002",
      "architecture": "planar_mosfet",
      "architecture_label": "Planar MOSFET",
      "scaling_context": "relaxed_electrostatic_baseline",
      "scaling_context_label": "Relaxed electrostatic baseline",
      "contact_strategy": "conventional_frontside_mol",
      "contact_strategy_label": "Conventional frontside MOL",
      "variability_mode": "edge_cd_variation",
      "variability_mode_label": "Edge and CD variation",
      "circuit_context": "inverter_chain",
      "circuit_context_label": "Inverter chain",
      "review_posture": "normalized_teaching_proxy",
      "review_posture_label": "Normalized teaching proxy",
      "electrostatic_control_score": "68.75",
      "drive_per_footprint_proxy": "43.25",
      "capacitance_burden_proxy": "28.75",
      "contact_resistance_burden_proxy": "28.00",
      "variability_sensitivity_proxy": "41.25",
      "thermal_coupling_proxy": "16.25",
      "integration_risk_proxy": "15.00",
      "evidence_maturity_score": "70.62",
      "circuit_handoff_readiness_score": "74.39",
      "comparison_readiness_score": "66.54",
      "decision_gate": "bounded_teaching_case",
      "evidence_state": "bounded teaching case",
      "next_safe_check": "use for lesson planning and keep replacement-evidence requirements visible",
      "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; single-path delay and slew handoff"
    },
    {
      "case_id": "ARCHCMP-0003",
      "architecture": "planar_mosfet",
      "architecture_label": "Planar MOSFET",
      "scaling_context": "relaxed_electrostatic_baseline",
      "scaling_context_label": "Relaxed electrostatic baseline",
      "contact_strategy": "conventional_frontside_mol",
      "contact_strategy_label": "Conventional frontside MOL",
      "variability_mode": "edge_cd_variation",
      "variability_mode_label": "Edge and CD variation",
      "circuit_context": "inverter_chain",
      "circuit_context_label": "Inverter chain",
      "review_posture": "cross_domain_review_packet",
      "review_posture_label": "Cross-domain review packet",
      "electrostatic_control_score": "68.75",
      "drive_per_footprint_proxy": "43.25",
      "capacitance_burden_proxy": "28.75",
      "contact_resistance_burden_proxy": "28.00",
      "variability_sensitivity_proxy": "41.25",
      "thermal_coupling_proxy": "16.25",
      "integration_risk_proxy": "15.00",
      "evidence_maturity_score": "79.17",
      "circuit_handoff_readiness_score": "75.08",
      "comparison_readiness_score": "76.15",
      "decision_gate": "bounded_comparison_case",
      "evidence_state": "bounded contextual comparison case",
      "next_safe_check": "use only as a contextual teaching comparison with all non-ranking limits attached",
      "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; single-path delay and slew handoff"
    },
    {
      "case_id": "ARCHCMP-0004",
      "architecture": "planar_mosfet",
      "architecture_label": "Planar MOSFET",
      "scaling_context": "relaxed_electrostatic_baseline",
      "scaling_context_label": "Relaxed electrostatic baseline",
      "contact_strategy": "conventional_frontside_mol",
      "contact_strategy_label": "Conventional frontside MOL",
      "variability_mode": "edge_cd_variation",
      "variability_mode_label": "Edge and CD variation",
      "circuit_context": "inverter_chain",
      "circuit_context_label": "Inverter chain",
      "review_posture": "replacement_evidence_plan",
      "review_posture_label": "Replacement-evidence plan",
      "electrostatic_control_score": "68.75",
      "drive_per_footprint_proxy": "43.25",
      "capacitance_burden_proxy": "28.75",
      "contact_resistance_burden_proxy": "28.00",
      "variability_sensitivity_proxy": "41.25",
      "thermal_coupling_proxy": "16.25",
      "integration_risk_proxy": "15.00",
      "evidence_maturity_score": "85.44",
      "circuit_handoff_readiness_score": "75.58",
      "comparison_readiness_score": "81.33",
      "decision_gate": "bounded_comparison_case",
      "evidence_state": "bounded contextual comparison case",
      "next_safe_check": "use only as a contextual teaching comparison with all non-ranking limits attached",
      "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; single-path delay and slew handoff"
    },
    {
      "case_id": "ARCHCMP-0005",
      "architecture": "planar_mosfet",
      "architecture_label": "Planar MOSFET",
      "scaling_context": "relaxed_electrostatic_baseline",
      "scaling_context_label": "Relaxed electrostatic baseline",
      "contact_strategy": "conventional_frontside_mol",
      "contact_strategy_label": "Conventional frontside MOL",
      "variability_mode": "edge_cd_variation",
      "variability_mode_label": "Edge and CD variation",
      "circuit_context": "local_clock_buffer",
      "circuit_context_label": "Local clock buffer",
      "review_posture": "architecture_vocabulary_only",
      "review_posture_label": "Architecture vocabulary only",
      "electrostatic_control_score": "68.75",
      "drive_per_footprint_proxy": "45.25",
      "capacitance_burden_proxy": "37.75",
      "contact_resistance_burden_proxy": "31.00",
      "variability_sensitivity_proxy": "44.25",
      "thermal_coupling_proxy": "20.25",
      "integration_risk_proxy": "18.00",
      "evidence_maturity_score": "62.64",
      "circuit_handoff_readiness_score": "65.72",
      "comparison_readiness_score": "54.65",
      "decision_gate": "owner_review_required",
      "evidence_state": "cross-domain owner review required",
      "next_safe_check": "route to device, integration, extraction, and circuit owners before any architecture claim",
      "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; capacitance, slew, and switching-power sensitivity"
    },
    {
      "case_id": "ARCHCMP-0006",
      "architecture": "planar_mosfet",
      "architecture_label": "Planar MOSFET",
      "scaling_context": "relaxed_electrostatic_baseline",
      "scaling_context_label": "Relaxed electrostatic baseline",
      "contact_strategy": "conventional_frontside_mol",
      "contact_strategy_label": "Conventional frontside MOL",
      "variability_mode": "edge_cd_variation",
      "variability_mode_label": "Edge and CD variation",
      "circuit_context": "local_clock_buffer",
      "circuit_context_label": "Local clock buffer",
      "review_posture": "normalized_teaching_proxy",
      "review_posture_label": "Normalized teaching proxy",
      "electrostatic_control_score": "68.75",
      "drive_per_footprint_proxy": "45.25",
      "capacitance_burden_proxy": "37.75",
      "contact_resistance_burden_proxy": "31.00",
      "variability_sensitivity_proxy": "44.25",
      "thermal_coupling_proxy": "20.25",
      "integration_risk_proxy": "18.00",
      "evidence_maturity_score": "70.62",
      "circuit_handoff_readiness_score": "66.36",
      "comparison_readiness_score": "63.15",
      "decision_gate": "bounded_teaching_case",
      "evidence_state": "bounded teaching case",
      "next_safe_check": "use for lesson planning and keep replacement-evidence requirements visible",
      "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; capacitance, slew, and switching-power sensitivity"
    },
    {
      "case_id": "ARCHCMP-0007",
      "architecture": "planar_mosfet",
      "architecture_label": "Planar MOSFET",
      "scaling_context": "relaxed_electrostatic_baseline",
      "scaling_context_label": "Relaxed electrostatic baseline",
      "contact_strategy": "conventional_frontside_mol",
      "contact_strategy_label": "Conventional frontside MOL",
      "variability_mode": "edge_cd_variation",
      "variability_mode_label": "Edge and CD variation",
      "circuit_context": "local_clock_buffer",
      "circuit_context_label": "Local clock buffer",
      "review_posture": "cross_domain_review_packet",
      "review_posture_label": "Cross-domain review packet",
      "electrostatic_control_score": "68.75",
      "drive_per_footprint_proxy": "45.25",
      "capacitance_burden_proxy": "37.75",
      "contact_resistance_burden_proxy": "31.00",
      "variability_sensitivity_proxy": "44.25",
      "thermal_coupling_proxy": "20.25",
      "integration_risk_proxy": "18.00",
      "evidence_maturity_score": "79.17",
      "circuit_handoff_readiness_score": "67.05",
      "comparison_readiness_score": "72.76",
      "decision_gate": "bounded_comparison_case",
      "evidence_state": "bounded contextual comparison case",
      "next_safe_check": "use only as a contextual teaching comparison with all non-ranking limits attached",
      "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; capacitance, slew, and switching-power sensitivity"
    },
    {
      "case_id": "ARCHCMP-0008",
      "architecture": "planar_mosfet",
      "architecture_label": "Planar MOSFET",
      "scaling_context": "relaxed_electrostatic_baseline",
      "scaling_context_label": "Relaxed electrostatic baseline",
      "contact_strategy": "conventional_frontside_mol",
      "contact_strategy_label": "Conventional frontside MOL",
      "variability_mode": "edge_cd_variation",
      "variability_mode_label": "Edge and CD variation",
      "circuit_context": "local_clock_buffer",
      "circuit_context_label": "Local clock buffer",
      "review_posture": "replacement_evidence_plan",
      "review_posture_label": "Replacement-evidence plan",
      "electrostatic_control_score": "68.75",
      "drive_per_footprint_proxy": "45.25",
      "capacitance_burden_proxy": "37.75",
      "contact_resistance_burden_proxy": "31.00",
      "variability_sensitivity_proxy": "44.25",
      "thermal_coupling_proxy": "20.25",
      "integration_risk_proxy": "18.00",
      "evidence_maturity_score": "85.44",
      "circuit_handoff_readiness_score": "67.55",
      "comparison_readiness_score": "77.94",
      "decision_gate": "bounded_comparison_case",
      "evidence_state": "bounded contextual comparison case",
      "next_safe_check": "use only as a contextual teaching comparison with all non-ranking limits attached",
      "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; capacitance, slew, and switching-power sensitivity"
    },
    {
      "case_id": "ARCHCMP-0009",
      "architecture": "planar_mosfet",
      "architecture_label": "Planar MOSFET",
      "scaling_context": "relaxed_electrostatic_baseline",
      "scaling_context_label": "Relaxed electrostatic baseline",
      "contact_strategy": "conventional_frontside_mol",
      "contact_strategy_label": "Conventional frontside MOL",
      "variability_mode": "edge_cd_variation",
      "variability_mode_label": "Edge and CD variation",
      "circuit_context": "sram_edge_peripheral",
      "circuit_context_label": "SRAM edge peripheral",
      "review_posture": "architecture_vocabulary_only",
      "review_posture_label": "Architecture vocabulary only",
      "electrostatic_control_score": "68.75",
      "drive_per_footprint_proxy": "42.25",
      "capacitance_burden_proxy": "32.75",
      "contact_resistance_burden_proxy": "33.00",
      "variability_sensitivity_proxy": "50.25",
      "thermal_coupling_proxy": "19.25",
      "integration_risk_proxy": "20.00",
      "evidence_maturity_score": "62.64",
      "circuit_handoff_readiness_score": "62.87",
      "comparison_readiness_score": "53.42",
      "decision_gate": "owner_review_required",
      "evidence_state": "cross-domain owner review required",
      "next_safe_check": "route to device, integration, extraction, and circuit owners before any architecture claim",
      "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; local routing, matching, and decision-margin sensitivity"
    },
    {
      "case_id": "ARCHCMP-0010",
      "architecture": "planar_mosfet",
      "architecture_label": "Planar MOSFET",
      "scaling_context": "relaxed_electrostatic_baseline",
      "scaling_context_label": "Relaxed electrostatic baseline",
      "contact_strategy": "conventional_frontside_mol",
      "contact_strategy_label": "Conventional frontside MOL",
      "variability_mode": "edge_cd_variation",
      "variability_mode_label": "Edge and CD variation",
      "circuit_context": "sram_edge_peripheral",
      "circuit_context_label": "SRAM edge peripheral",
      "review_posture": "normalized_teaching_proxy",
      "review_posture_label": "Normalized teaching proxy",
      "electrostatic_control_score": "68.75",
      "drive_per_footprint_proxy": "42.25",
      "capacitance_burden_proxy": "32.75",
      "contact_resistance_burden_proxy": "33.00",
      "variability_sensitivity_proxy": "50.25",
      "thermal_coupling_proxy": "19.25",
      "integration_risk_proxy": "20.00",
      "evidence_maturity_score": "70.62",
      "circuit_handoff_readiness_score": "63.51",
      "comparison_readiness_score": "61.93",
      "decision_gate": "owner_review_required",
      "evidence_state": "cross-domain owner review required",
      "next_safe_check": "route to device, integration, extraction, and circuit owners before any architecture claim",
      "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; local routing, matching, and decision-margin sensitivity"
    },
    {
      "case_id": "ARCHCMP-0011",
      "architecture": "planar_mosfet",
      "architecture_label": "Planar MOSFET",
      "scaling_context": "relaxed_electrostatic_baseline",
      "scaling_context_label": "Relaxed electrostatic baseline",
      "contact_strategy": "conventional_frontside_mol",
      "contact_strategy_label": "Conventional frontside MOL",
      "variability_mode": "edge_cd_variation",
      "variability_mode_label": "Edge and CD variation",
      "circuit_context": "sram_edge_peripheral",
      "circuit_context_label": "SRAM edge peripheral",
      "review_posture": "cross_domain_review_packet",
      "review_posture_label": "Cross-domain review packet",
      "electrostatic_control_score": "68.75",
      "drive_per_footprint_proxy": "42.25",
      "capacitance_burden_proxy": "32.75",
      "contact_resistance_burden_proxy": "33.00",
      "variability_sensitivity_proxy": "50.25",
      "thermal_coupling_proxy": "19.25",
      "integration_risk_proxy": "20.00",
      "evidence_maturity_score": "79.17",
      "circuit_handoff_readiness_score": "64.20",
      "comparison_readiness_score": "71.54",
      "decision_gate": "bounded_teaching_case",
      "evidence_state": "bounded teaching case",
      "next_safe_check": "use for lesson planning and keep replacement-evidence requirements visible",
      "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; local routing, matching, and decision-margin sensitivity"
    },
    {
      "case_id": "ARCHCMP-0012",
      "architecture": "planar_mosfet",
      "architecture_label": "Planar MOSFET",
      "scaling_context": "relaxed_electrostatic_baseline",
      "scaling_context_label": "Relaxed electrostatic baseline",
      "contact_strategy": "conventional_frontside_mol",
      "contact_strategy_label": "Conventional frontside MOL",
      "variability_mode": "edge_cd_variation",
      "variability_mode_label": "Edge and CD variation",
      "circuit_context": "sram_edge_peripheral",
      "circuit_context_label": "SRAM edge peripheral",
      "review_posture": "replacement_evidence_plan",
      "review_posture_label": "Replacement-evidence plan",
      "electrostatic_control_score": "68.75",
      "drive_per_footprint_proxy": "42.25",
      "capacitance_burden_proxy": "32.75",
      "contact_resistance_burden_proxy": "33.00",
      "variability_sensitivity_proxy": "50.25",
      "thermal_coupling_proxy": "19.25",
      "integration_risk_proxy": "20.00",
      "evidence_maturity_score": "85.44",
      "circuit_handoff_readiness_score": "64.70",
      "comparison_readiness_score": "76.72",
      "decision_gate": "bounded_comparison_case",
      "evidence_state": "bounded contextual comparison case",
      "next_safe_check": "use only as a contextual teaching comparison with all non-ranking limits attached",
      "teaching_readout": "single-plane gate and mature device-to-circuit handoff context; frontside contact and local-interconnect baseline; pattern edge and critical-dimension sensitivity; local routing, matching, and decision-margin sensitivity"
    }
  ],
  "sources": [
    {
      "label": "IBM Research: Toward ultimate scaling of MOSFET",
      "url": "https://research.ibm.com/publications/toward-ultimate-scaling-of-mosfet",
      "note": "Research metadata anchoring planar-MOSF and FinFET electrostatic comparison vocabulary. No paper body, figure, model, or table is copied."
    },
    {
      "label": "imec: Entering the nanosheet transistor era",
      "url": "https://www.imec-int.com/en/articles/entering-nanosheet-transistor-era-0",
      "note": "Official public reading-room article anchoring FinFET-to-GAA nanosheet control, width, capacitance, and variability context."
    },
    {
      "label": "IBM Research: Stacked nanosheet GAA transistor",
      "url": "https://research.ibm.com/publications/stacked-nanosheet-gate-all-around-transistor-to-enable-scaling-beyond-finfet",
      "note": "Research metadata anchoring stacked-nanosheet GAA electrostatics, effective width, and contact vocabulary."
    },
    {
      "label": "imec: A view on the logic technology roadmap",
      "url": "https://www.imec-int.com/en/articles/view-logic-technology-roadmap",
      "note": "Official roadmap article connecting FEOL architecture, MOL contacts, local interconnect, routability, and DTCO context."
    },
    {
      "label": "imec: CFET on the logic technology roadmap",
      "url": "https://www.imec-int.com/en/articles/imec-puts-complementary-fet-cfet-logic-technology-roadmap",
      "note": "Official public CFET article anchoring monolithic and sequential stacking plus integration-complexity vocabulary."
    },
    {
      "label": "IRDS: More Moore device characteristics",
      "url": "https://irds.ieee.org/images/files/pdf/Technical_Articles/More_Moore_with_BC_and_CEQIP.pdf",
      "note": "Public roadmap document anchoring architecture inflection, PPAC, 3D integration, thermal, and metrology context."
    },
    {
      "label": "NIST: Metrology for next-generation semiconductor devices",
      "url": "https://www.nist.gov/publications/metrology-next-generation-semiconductor-devices",
      "note": "Official publication record anchoring dimensional-metrology and complex-3D-device measurement limits."
    },
    {
      "label": "Synopsys: GAA to CFET transistor scaling",
      "url": "https://www.synopsys.com/blogs/chip-design/gate-all-around-complementary-fets-whats-next-transistor-scaling.html",
      "note": "Official public technology article anchoring planar, FinFET, GAA, and CFET coexistence plus device-to-design handoff vocabulary."
    }
  ],
  "public_boundary": [
    "No live TCAD, SPICE, compact-model fitting, parasitic extraction, electrothermal solving, process simulation, or architecture optimizer runs in the browser or on the server.",
    "No PDK, compact model, TCAD deck, process flow, layout, extraction technology file, standard-cell library, measured silicon, vendor benchmark, roadmap table, or source figure is copied.",
    "No architecture, foundry node, vendor, product, or process is ranked; no signoff, qualification, readiness, cost, yield, or production recommendation is made.",
    "Rows are original normalized teaching proxies. Engineering reuse requires owned calibrated device models, I-V/C-V, geometry and variability metrology, contact/local-RC extraction, thermal evidence, circuit correlation, and cross-domain owner review."
  ],
  "limitations": [
    "Numeric values are normalized contextual proxies, not physical units or calibrated comparisons.",
    "Architecture effects are intentionally coupled to scaling, contact, variability, circuit, and evidence context; a single score must not be read as a universal winner.",
    "Source links are outbound vocabulary and evidence anchors only. External text, figures, tables, models, layouts, data, and code remain with their rights holders."
  ]
}