{
  "schema": "semiagora.process-device-yield-source-spine.v1",
  "version": "2026-08-30-process-device-yield-v1",
  "experimentId": "SA-INT-PROCESS-DEVICE-YIELD-042",
  "generatedAt": "2026-08-30T00:00:00+09:00",
  "sourceBodiesStored": false,
  "sourceNumericUse": "none",
  "rightsMode": "link-only",
  "sourceCount": 20,
  "claimNodeCount": 16,
  "inputHashesSha256": {
    "process-device-yield-state-contract-v1.json": "D713FCF45B95060FA61D210915EF6F9B7CC1871D1F88FE40B5939517D7928970",
    "process-device-yield-metric-contract-v1.json": "7FFAB5809FC57C1DDEE88FA04DCFC9A05280BA31D3EC732AB6E3BBC27A216E57",
    "source_catalog_v1.json": "E8DDC6A9DED9BD0E32FA92F77E39AB427F4071E2528F3D8EE8A20BAE50CBA164",
    "source_claim_map_v1.json": "E562E345D62DFB0697752ED95977EEE91AE024A975F723B65AB9C65B48DE5663",
    "independent-verifier-contract-v1.json": "50F9CB769BA895E974F4F7BBE6C5C53D914F0BAE02D855BB9AFE020685ACC216"
  },
  "sources": [
    {
      "id": "semi-traceability",
      "label": "SEMI Standards: Traceability",
      "publisher": "SEMI",
      "url": "https://www.semi.org/en/products-services/standards/traceability",
      "sourceType": "official-standards-topic-page-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for device, manufacturing, test, assembly, and supply-chain traceability boundaries.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "semi-information-control",
      "label": "SEMI Standards: Information and Control",
      "publisher": "SEMI",
      "url": "https://www.semi.org/en/products-services/standards/information_and_control",
      "sourceType": "official-standards-topic-page-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for substrate tracking, equipment quality, advanced process control, data collection, and mapping vocabulary families.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "semi-t23-single-device-traceability",
      "label": "SEMI T23 - Specification for Single Device Traceability for the Supply Chain",
      "publisher": "SEMI",
      "url": "https://store-us.semi.org/products/t02300-semi-t23-specification-for-single-device-traceability-for-the-supply-chain",
      "sourceType": "official-standard-page-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for single-device identity and supply-chain traceability boundaries.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "nist-chips-metrology-program",
      "label": "NIST CHIPS Metrology Program",
      "publisher": "National Institute of Standards and Technology",
      "url": "https://www.nist.gov/chips/research-development-programs/metrology-program",
      "sourceType": "official-program-page-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for semiconductor metrology, measurement assurance, reference methods, and standards needs.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "irds-2024-metrology",
      "label": "2024 International Roadmap for Devices and Systems: Metrology",
      "publisher": "IEEE IRDS / NIST",
      "url": "https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=959302",
      "sourceType": "official-roadmap-pdf-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level roadmap provenance for semiconductor metrology, characterization, uncertainty, and cross-domain measurement challenges.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "irds-2023-factory-integration",
      "label": "2023 International Roadmap for Devices and Systems: Factory Integration",
      "publisher": "IEEE IRDS",
      "url": "https://irds.ieee.org/images/files/pdf/2023/2023IRDS_FAC.pdf",
      "sourceType": "official-roadmap-pdf-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level roadmap provenance for factory integration, data, equipment, traceability, and manufacturing-system boundaries.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "analog-process-sensitivity-yield-2022",
      "label": "Modeling the Dependency of Analog Circuit Performance Parameters on Manufacturing Process Variations With Applications in Sensitivity Analysis and Yield Prediction",
      "publisher": "IEEE",
      "url": "https://doi.org/10.1109/TCAD.2021.3054804",
      "sourceType": "peer-reviewed-journal-metadata-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for process-parameter dependency, circuit sensitivity, and yield-prediction boundaries.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "mos-matching-1989",
      "label": "Matching Properties of MOS Transistors",
      "publisher": "IEEE",
      "url": "https://doi.org/10.1109/JSSC.1989.572629",
      "sourceType": "peer-reviewed-journal-metadata-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for local device mismatch and statistical parameter-variation boundaries.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "random-dopant-threshold-1998",
      "label": "Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Sub-0.1 Micrometer MOSFETs: A 3-D Atomistic Simulation Study",
      "publisher": "IEEE",
      "url": "https://doi.org/10.1109/16.735728",
      "sourceType": "peer-reviewed-journal-metadata-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for atomistic random-dopant and threshold-voltage variability boundaries.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "die-within-die-frequency-2002",
      "label": "Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration",
      "publisher": "IEEE",
      "url": "https://doi.org/10.1109/4.982424",
      "sourceType": "peer-reviewed-journal-metadata-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for die-to-die, within-die, and circuit-frequency variation boundaries.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "random-dopant-delay-2005",
      "label": "Estimation of Delay Variations Due to Random-Dopant Fluctuations in Nanoscale CMOS Circuits",
      "publisher": "IEEE",
      "url": "https://doi.org/10.1109/JSSC.2005.852164",
      "sourceType": "peer-reviewed-journal-metadata-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for device random variation and downstream circuit-delay boundaries.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "trigate-process-variability-2013",
      "label": "Comparative Simulation Analysis of Process-Induced Variability in Nanoscale SOI and Bulk Trigate FinFETs",
      "publisher": "IEEE",
      "url": "https://doi.org/10.1109/TED.2013.2281474",
      "sourceType": "peer-reviewed-journal-metadata-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for process-induced variability and device-architecture applicability boundaries.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "finfet-random-variation-sources-2016",
      "label": "A Device-Level Characterization Approach to Quantify the Impacts of Different Random Variation Sources in FinFET Technology",
      "publisher": "IEEE",
      "url": "https://doi.org/10.1109/LED.2016.2581878",
      "sourceType": "peer-reviewed-journal-metadata-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for device-level separation of random variation-source families.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "spatial-variation-decomposition-1997",
      "label": "Analysis and Decomposition of Spatial Variation in Integrated Circuit Processes and Devices",
      "publisher": "IEEE",
      "url": "https://doi.org/10.1109/66.554480",
      "sourceType": "peer-reviewed-journal-metadata-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for spatial variation decomposition across process and device observations.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "systematic-gate-length-circuit-2000",
      "label": "Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits",
      "publisher": "IEEE / ACM",
      "url": "https://doi.org/10.1109/ICCAD.2000.896452",
      "sourceType": "peer-reviewed-proceedings-metadata-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for systematic spatial process variation and circuit-performance boundaries.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "statistical-sram-stability-2006",
      "label": "Statistical Analysis of SRAM Cell Stability",
      "publisher": "ACM",
      "url": "https://doi.org/10.1145/1146909.1146928",
      "sourceType": "peer-reviewed-proceedings-metadata-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for SRAM stability, process variation, and statistical yield boundaries.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "vlsi-artwork-yield-1983",
      "label": "Yield Estimation Model for VLSI Artwork Evaluation",
      "publisher": "IET",
      "url": "https://doi.org/10.1049/el:19830156",
      "sourceType": "peer-reviewed-journal-metadata-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for defect-sensitive artwork and yield-estimation model boundaries.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "spatial-correlation-timing-2005",
      "label": "Statistical Timing Analysis Under Spatial Correlations",
      "publisher": "IEEE",
      "url": "https://doi.org/10.1109/TCAD.2005.850834",
      "sourceType": "peer-reviewed-journal-metadata-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for spatial correlation and statistical timing-analysis boundaries.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "delay-variability-test-structures-2002",
      "label": "Test Structures for Delay Variability",
      "publisher": "ACM / IEEE",
      "url": "https://doi.org/10.1145/589411.589435",
      "sourceType": "peer-reviewed-proceedings-metadata-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for test structures and measured delay-variability boundaries.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    },
    {
      "id": "adaptive-body-bias-variation-2002",
      "label": "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage",
      "publisher": "IEEE",
      "url": "https://doi.org/10.1109/JSSC.2002.803949",
      "sourceType": "peer-reviewed-journal-metadata-record",
      "rightsStatus": "link-only",
      "numericUse": "none",
      "use": "Category-level provenance for circuit adaptation, frequency, leakage, and variation-response boundaries.",
      "artifactUse": "Link-only metadata and category-level provenance. No source body, abstract wording, numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision enters generated artifacts."
    }
  ],
  "claims": [
    {
      "node_id": "PDY-C01",
      "claim": "Process-device-yield integration keeps process-module, process-device, device-circuit, reliability-yield, and public-handoff boundaries explicit.",
      "source_ids": [
        "semi-traceability",
        "nist-chips-metrology-program",
        "irds-2023-factory-integration",
        "analog-process-sensitivity-yield-2022"
      ],
      "boundary": "No source body, abstract wording, source numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, result, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision is imported."
    },
    {
      "node_id": "PDY-C02",
      "claim": "Film, profile, interface, contact, and equipment-lineage variation families remain distinct until owned evidence supports a causal join.",
      "source_ids": [
        "irds-2024-metrology",
        "spatial-variation-decomposition-1997",
        "trigate-process-variability-2013",
        "finfet-random-variation-sources-2016"
      ],
      "boundary": "No source body, abstract wording, source numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, result, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision is imported."
    },
    {
      "node_id": "PDY-C03",
      "claim": "Device-characterization, circuit-margin, and reliability-yield observations require traceable context before cross-domain comparison.",
      "source_ids": [
        "semi-information-control",
        "nist-chips-metrology-program",
        "analog-process-sensitivity-yield-2022",
        "delay-variability-test-structures-2002"
      ],
      "boundary": "No source body, abstract wording, source numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, result, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision is imported."
    },
    {
      "node_id": "PDY-C04",
      "claim": "Random, systematic, spatial, die-to-die, and within-die variation categories are not interchangeable.",
      "source_ids": [
        "mos-matching-1989",
        "die-within-die-frequency-2002",
        "spatial-variation-decomposition-1997",
        "systematic-gate-length-circuit-2000"
      ],
      "boundary": "No source body, abstract wording, source numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, result, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision is imported."
    },
    {
      "node_id": "PDY-C05",
      "claim": "Device variability evidence requires owned structure, bias, temperature, method, uncertainty, and model-applicability context.",
      "source_ids": [
        "random-dopant-threshold-1998",
        "trigate-process-variability-2013",
        "finfet-random-variation-sources-2016",
        "irds-2024-metrology"
      ],
      "boundary": "No source body, abstract wording, source numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, result, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision is imported."
    },
    {
      "node_id": "PDY-C06",
      "claim": "Device-to-circuit transfer requires bounded sensitivity and model evidence rather than an automatic mapping from process labels.",
      "source_ids": [
        "analog-process-sensitivity-yield-2022",
        "random-dopant-delay-2005",
        "die-within-die-frequency-2002",
        "adaptive-body-bias-variation-2002"
      ],
      "boundary": "No source body, abstract wording, source numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, result, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision is imported."
    },
    {
      "node_id": "PDY-C07",
      "claim": "Local mismatch, spatial correlation, and hierarchical variation require separate ownership in circuit and yield evidence.",
      "source_ids": [
        "mos-matching-1989",
        "spatial-correlation-timing-2005",
        "spatial-variation-decomposition-1997",
        "systematic-gate-length-circuit-2000"
      ],
      "boundary": "No source body, abstract wording, source numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, result, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision is imported."
    },
    {
      "node_id": "PDY-C08",
      "claim": "Circuit delay, frequency, leakage, stability, and margin labels are contextual evidence categories, not design limits or signoff results.",
      "source_ids": [
        "die-within-die-frequency-2002",
        "random-dopant-delay-2005",
        "statistical-sram-stability-2006",
        "adaptive-body-bias-variation-2002"
      ],
      "boundary": "No source body, abstract wording, source numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, result, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision is imported."
    },
    {
      "node_id": "PDY-C09",
      "claim": "SRAM stability and statistical timing connect device variation to circuit evidence only under owned topology, workload, PVT, and correlation context.",
      "source_ids": [
        "statistical-sram-stability-2006",
        "spatial-correlation-timing-2005",
        "random-dopant-delay-2005"
      ],
      "boundary": "No source body, abstract wording, source numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, result, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision is imported."
    },
    {
      "node_id": "PDY-C10",
      "claim": "Test structures and metrology require traceable measurement-system, sampling, location, and uncertainty evidence before yield attribution.",
      "source_ids": [
        "nist-chips-metrology-program",
        "irds-2024-metrology",
        "delay-variability-test-structures-2002",
        "semi-information-control"
      ],
      "boundary": "No source body, abstract wording, source numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, result, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision is imported."
    },
    {
      "node_id": "PDY-C11",
      "claim": "Lot-wafer-die-device-test genealogy and map transforms are explicit replacement-evidence requirements for yield learning.",
      "source_ids": [
        "semi-traceability",
        "semi-t23-single-device-traceability",
        "semi-information-control",
        "irds-2023-factory-integration"
      ],
      "boundary": "No source body, abstract wording, source numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, result, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision is imported."
    },
    {
      "node_id": "PDY-C12",
      "claim": "Yield models require owned defect taxonomy, denominator, coverage, selection, confidence, and applicability evidence.",
      "source_ids": [
        "vlsi-artwork-yield-1983",
        "statistical-sram-stability-2006",
        "analog-process-sensitivity-yield-2022"
      ],
      "boundary": "No source body, abstract wording, source numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, result, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision is imported."
    },
    {
      "node_id": "PDY-C13",
      "claim": "PTCO and DTCO review must expose cross-domain objective, constraint, model fidelity, and uncertainty rather than collapse them into one score.",
      "source_ids": [
        "irds-2023-factory-integration",
        "irds-2024-metrology",
        "analog-process-sensitivity-yield-2022",
        "trigate-process-variability-2013"
      ],
      "boundary": "No source body, abstract wording, source numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, result, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision is imported."
    },
    {
      "node_id": "PDY-C14",
      "claim": "The normalized proxies and integer ledgers are source-independent teaching constructs and are not physical models, fits, specifications, or recommendations.",
      "source_ids": [
        "nist-chips-metrology-program",
        "semi-information-control",
        "spatial-variation-decomposition-1997"
      ],
      "boundary": "No source body, abstract wording, source numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, result, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision is imported."
    },
    {
      "node_id": "PDY-C15",
      "claim": "Packet outputs remain categorical evidence handoffs to the public atlas and never become automatic control, calibration, qualification, signoff, publication, or disposition actions.",
      "source_ids": [
        "semi-traceability",
        "semi-information-control",
        "irds-2023-factory-integration"
      ],
      "boundary": "No source body, abstract wording, source numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, result, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision is imported."
    },
    {
      "node_id": "PDY-C16",
      "claim": "Every teaching label must be replaced by accountable process, measurement, device, model, circuit, reliability, test, genealogy, yield, uncertainty, and human-approval evidence before operational use.",
      "source_ids": [
        "semi-t23-single-device-traceability",
        "nist-chips-metrology-program",
        "irds-2024-metrology",
        "adaptive-body-bias-variation-2002"
      ],
      "boundary": "No source body, abstract wording, source numeric value, equation, coefficient, geometry, material property, process condition, measurement, model parameter, defect or yield value, method setting, specification limit, result, figure, table, code, image, model output, named-tool output, copied artifact, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision is imported."
    }
  ],
  "hardBoundary": "No source body, source numeric value, equation, coefficient, geometry, material property, process condition, method setting, measurement, model parameter, defect or yield value, result, automatic action, acceptance, qualification, signoff, publication, disposition, or production decision may enter generated artifacts."
}