{
  "schema": "semiagora.ptr-simulation.v1",
  "experiment_id": "SA-PTR-PKG-PARASITICS-001",
  "title": "Package parasitics RLC budget",
  "execution_mode": "precomputed-only",
  "model_boundary": "Educational package-parasitics replay for trend literacy; not a package extraction, package design, or signal/power-integrity signoff model.",
  "limitations": [
    "No product package design, package signoff, board design release, or production thermal-design decision is included.",
    "No ATE program, wafer-sort recipe, bin-limit release, test-time quote, or production screen is included.",
    "No JEDEC qualification, customer quality claim, reliability signoff, or device release statement is made.",
    "All numbers are educational teaching proxies and must be replaced by qualified measurements before engineering decisions."
  ],
  "sources": [
    {
      "label": "NIST National Advanced Packaging Manufacturing Program",
      "url": "https://www.nist.gov/chips/research-development-programs/national-advanced-packaging-manufacturing-program",
      "note": "Public NIST page framing advanced packaging challenges around power, heat, test, repair, and reliability."
    },
    {
      "label": "NIST advanced semiconductor packaging material needs",
      "url": "https://www.nist.gov/publications/material-needs-and-measurement-challenges-advanced-semiconductor-packaging",
      "note": "Public NIST publication page on packaging materials, metrology, moisture reliability, residual stress, warpage, and reproducibility."
    },
    {
      "label": "NIST reliability metrology for semiconductors",
      "url": "https://www.nist.gov/publications/reliability-metrology-semiconductor-industry-nist",
      "note": "Public NIST publication page anchoring reliability assessment as a semiconductor metrology concern."
    },
    {
      "label": "SEMI Heterogeneous Integration Roadmap",
      "url": "https://www.semi.org/en/communities/heterogeneous_integration_roadmap",
      "note": "Public roadmap page connecting assembly, packaging, interconnect, test, thermal management, and reliability."
    }
  ],
  "axes": [
    "package integration teaching case"
  ],
  "cases": [
    {
      "label": "wirebond_qfn_teaching_case",
      "interconnect_length_mm": 4.0,
      "loop_inductance_pH": 3200,
      "coupling_capacitance_fF": 110,
      "signal_delay_ps": 22,
      "pdn_impedance_mOhm": 180
    },
    {
      "label": "flip_chip_bga_teaching_case",
      "interconnect_length_mm": 1.2,
      "loop_inductance_pH": 520,
      "coupling_capacitance_fF": 180,
      "signal_delay_ps": 11,
      "pdn_impedance_mOhm": 92
    },
    {
      "label": "interposer_2p5d_teaching_case",
      "interconnect_length_mm": 0.45,
      "loop_inductance_pH": 180,
      "coupling_capacitance_fF": 260,
      "signal_delay_ps": 7,
      "pdn_impedance_mOhm": 55
    },
    {
      "label": "chiplet_3d_teaching_case",
      "interconnect_length_mm": 0.12,
      "loop_inductance_pH": 80,
      "coupling_capacitance_fF": 420,
      "signal_delay_ps": 5,
      "pdn_impedance_mOhm": 38
    }
  ],
  "derived_metrics": {
    "interposer_inductance_pH": 180,
    "chiplet_3d_signal_delay_ps": 5,
    "wirebond_to_3d_inductance_reduction_percent": 97.5
  },
  "verification": {
    "case_count": 4,
    "inductance_decreases_with_integration": true,
    "signal_delay_decreases": true,
    "pdn_impedance_decreases": true,
    "all_cases_precomputed": true
  }
}