* SemiAgora V129 original RC step evidence circuit
* Rights: original project-authored netlist, CC0-style project reuse intended
* Model boundary: ideal independent source, linear resistor, ideal capacitor
VSTEP in 0 PULSE(0 1 0 1p 1p 20n 40n)
RPATH in out 1k
CLOAD out 0 1p IC=0
.options reltol=1e-6 abstol=1e-12 vntol=1e-9 itl1=100 itl4=100
.tran 5p 5n 0 5p UIC
.control
set wr_vecnames
set wr_singlescale
run
wrdata rc_step_reference.csv time v(in) v(out)
quit
.endc
.end