{
  "schema": "semiagora.sram-memory-depth.v1",
  "version": "2026-08-12-v60",
  "experiment_id": "SA-MEM-DEPTH-CACHE-001",
  "title": "Cache behavior replay for SRAM latency intuition",
  "execution_mode": "precomputed-only",
  "model_boundary": "Educational replay built from rights-clean synthetic and analytic data. It is not a measured macro, post-layout SRAM, foundry characterization, or product signoff result.",
  "metric_contract": {
    "name": "average memory access time replay",
    "input_axes": [
      "access pattern",
      "L1 miss rate",
      "L2 local miss rate",
      "miss penalty"
    ],
    "observation": "AMAT = L1 hit time + L1 miss rate*(L2 hit time + L2 local miss rate*memory penalty)",
    "pass_rule": "lower AMAT means the workload is less exposed to deeper memory hierarchy latency"
  },
  "cases": [
    {
      "id": "cache-blocked",
      "pattern": "blocked tile",
      "l1_hit_time_cycles": 1,
      "l1_miss_rate": 0.015,
      "l2_hit_time_cycles": 8,
      "l2_local_miss_rate": 0.15,
      "memory_penalty_cycles": 180,
      "amat_cycles": 1.52,
      "interpretation": "cache-friendly"
    },
    {
      "id": "cache-sequential",
      "pattern": "sequential scan",
      "l1_hit_time_cycles": 1,
      "l1_miss_rate": 0.03,
      "l2_hit_time_cycles": 8,
      "l2_local_miss_rate": 0.2,
      "memory_penalty_cycles": 180,
      "amat_cycles": 2.32,
      "interpretation": "cache-friendly"
    },
    {
      "id": "cache-strided",
      "pattern": "large stride",
      "l1_hit_time_cycles": 1,
      "l1_miss_rate": 0.18,
      "l2_hit_time_cycles": 8,
      "l2_local_miss_rate": 0.35,
      "memory_penalty_cycles": 180,
      "amat_cycles": 13.78,
      "interpretation": "memory-sensitive"
    },
    {
      "id": "cache-random",
      "pattern": "random pointer walk",
      "l1_hit_time_cycles": 1,
      "l1_miss_rate": 0.35,
      "l2_hit_time_cycles": 8,
      "l2_local_miss_rate": 0.6,
      "memory_penalty_cycles": 180,
      "amat_cycles": 41.6,
      "interpretation": "memory-bound"
    },
    {
      "id": "cache-thrashing",
      "pattern": "conflict thrash",
      "l1_hit_time_cycles": 1,
      "l1_miss_rate": 0.5,
      "l2_hit_time_cycles": 8,
      "l2_local_miss_rate": 0.7,
      "memory_penalty_cycles": 180,
      "amat_cycles": 68,
      "interpretation": "memory-bound"
    }
  ],
  "derived_metrics": {
    "case_count": 5,
    "best_amat_cycles": 1.52,
    "worst_amat_cycles": 68,
    "random_to_blocked_ratio": 27.37,
    "thrash_to_blocked_ratio": 44.74
  },
  "verification": {
    "amat_matches_recursive_formula": true,
    "higher_miss_rates_increase_amat": true,
    "access_pattern_is_separate_from_bitcell_timing": true,
    "no_private_trace_or_user_upload_is_used": true
  },
  "limitations": [
    "This replay uses synthetic workload patterns and educational cycle counts, not measured CPU performance.",
    "It connects SRAM/cache vocabulary to memory hierarchy behavior; it does not model a specific processor, cache controller, compiler, or DRAM timing.",
    "The model ignores coherence traffic, prefetching, write policy, TLB effects, bank conflicts, and queueing.",
    "System-level cache conclusions must not be used as evidence for a transistor-level SRAM macro without separate timing data."
  ],
  "sources": [
    {
      "label": "UCLA eScholarship SRAM sense amplifier thesis",
      "url": "https://escholarship.org/content/qt0xn2r2wx/qt0xn2r2wx_noSplash_78b1af6aa1f3f19975d8ea05d02b6c16.pdf",
      "note": "Public thesis used for offset, attenuation, control-timing, and sense-amplifier vocabulary."
    },
    {
      "label": "Grossar et al. SRAM read stability and write-ability",
      "url": "https://lirias.kuleuven.be/retrieve/109654",
      "note": "Public paper used for read-stability, write-ability, SNM, and N-curve vocabulary."
    },
    {
      "label": "NVIDIA reverse write assist and SRAM VMIN paper",
      "url": "https://research.nvidia.com/sites/default/files/pubs/2014-03_A-Reverse-Write/ISQED14.pdf",
      "note": "Public paper used to anchor assist, reverse assist, VMIN, guardband, and canary vocabulary."
    },
    {
      "label": "CS61C average memory access time notes",
      "url": "https://notes.cs61c.org/content/caches-intro/amat/",
      "note": "Public course note used for hit time, miss rate, miss penalty, and AMAT vocabulary."
    }
  ]
}