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"transfer_efficiency": "0.7793", "shared_common_mode_sample_v": "0.9165", "latency_mux_to_dout50_ps": "484", "unselected_disturb_mv": "1.288", "energy_fj": "0.1754", "label": "pass" }, { "case_index": 861, "case_id": "mem017_0861_v0p9_m8_d256_x4_l14_clean", "vdd_v": "0.9", "mux_ratio": "8", "bitline_depth": "256", "mux_tx_scale": "4", "sense_load_ff": "14", "write_path_state": "clean", "local_diff_sample_mv": "17.555", "shared_diff_sample_mv": "13.317", "transfer_efficiency": "0.7586", "shared_common_mode_sample_v": "0.9162", "latency_mux_to_dout50_ps": "502", "unselected_disturb_mv": "1.255", "energy_fj": "0.2258", "label": "pass" }, { "case_index": 862, "case_id": "mem017_0862_v0p9_m8_d256_x4_l14_leaky", "vdd_v": "0.9", "mux_ratio": "8", "bitline_depth": "256", "mux_tx_scale": "4", "sense_load_ff": "14", "write_path_state": "leaky", "local_diff_sample_mv": "17.511", "shared_diff_sample_mv": "12.244", "transfer_efficiency": "0.6992", "shared_common_mode_sample_v": "0.9154", "latency_mux_to_dout50_ps": "536", "unselected_disturb_mv": "1.154", "energy_fj": "0.2487", "label": "late_io" }, { "case_index": 863, "case_id": "mem017_0863_v0p9_m8_d256_x4_l28_clean", "vdd_v": "0.9", "mux_ratio": "8", "bitline_depth": "256", "mux_tx_scale": "4", "sense_load_ff": "28", "write_path_state": "clean", "local_diff_sample_mv": "17.436", "shared_diff_sample_mv": "11.155", "transfer_efficiency": "0.6398", "shared_common_mode_sample_v": "0.9145", "latency_mux_to_dout50_ps": "580", "unselected_disturb_mv": "1.047", "energy_fj": "0.3721", "label": "late_io" }, { "case_index": 864, "case_id": "mem017_0864_v0p9_m8_d256_x4_l28_leaky", "vdd_v": "0.9", "mux_ratio": "8", "bitline_depth": "256", "mux_tx_scale": "4", "sense_load_ff": "28", "write_path_state": "leaky", "local_diff_sample_mv": "17.373", "shared_diff_sample_mv": "10.451", "transfer_efficiency": "0.6016", "shared_common_mode_sample_v": "0.9139", "latency_mux_to_dout50_ps": "606", "unselected_disturb_mv": "0.975", "energy_fj": "0.3958", "label": "late_io" } ], "qa": { "fixture": { "status": "PASS", "score": 13, "total": 13 }, "independentVerification": { "status": "PASS", "score": 10, "total": 10 } }, "methods": [ "Generate a deterministic 864-case transient grid over VDD, mux ratio, selected bitline depth, mux pass-device scale, shared sense/I/O load, and write-path off-state.", "Measure local bitline differential, shared sense differential, transfer efficiency, common-mode, output 50 percent crossing, unselected disturbance, energy, and outcome label.", "Independently reparse decks, raw waveforms, topology tokens, parameter grid, metrics, labels, and artifact hashes before promoting the browser replay." ], "limitations": [ "The fixture uses generic Level-1 MOS devices, lumped loads, and effective pass-device behavior.", "It is not calibrated macro timing, foundry evidence, silicon evidence, yield qualification, reliability signoff, or a product comparison.", "No live server solver execution or uploaded design/netlist ingestion; the public page filters saved rows only." ], "evidence": [ "Research QA passed 15/15 with 20 source records, 20 controlled claims, and 15 misconception corrections.", "Primary fixture QA passed 13/13 and independent no-import verification passed 10/10.", "The public CSV is generated from the verified 864-row metric table and keeps the same measurement contract." ], "sources": [ { "label": "OpenRAM architecture documentation", "url": "https://github.com/VLSIDA/OpenRAM/blob/stable/docs/source/architecture.md", "note": "Anchors the SRAM macro block boundary around decoders, column mux, precharge, sense amplifiers, write drivers, and control logic." }, { "label": "OpenRAM column mux module", "url": "https://github.com/VLSIDA/OpenRAM/blob/stable/compiler/modules/column_mux.py", "note": "Open-source reference for treating column muxing as selected pass devices between local bitlines and shared column circuitry." }, { "label": "OpenRAM: An Open-Source Memory Compiler", "url": "https://escholarship.org/content/qt8x19c778/qt8x19c778_noSplash_b2b3fbbb57f1269f86d0de77865b0691.pdf", "note": "Public compiler paper for SRAM module context; SemiAgora uses original teaching data and does not copy figures." }, { "label": "CACTI 7 memory modeling tool", "url": "https://users.cs.utah.edu/~rajeev/cacti7/", "note": "Anchors memory timing and array-peripheral tradeoff vocabulary at an analytical-tool level." }, { "label": "ngspice simulator documentation", "url": "https://ngspice.sourceforge.io/", "note": "Open simulator used for the PDK-free transient replay fixture." } ], "sourceCatalog": [ { "source_id": "MEM17-S01", "title": "OpenRAM project site", "source_type": "official project", "url": "https://openram.org/", "use": "Open SRAM compiler framing and public memory-generator context.", "rights_note": "Link and summarize only." }, { "source_id": "MEM17-S02", "title": "OpenRAM GitHub repository", "source_type": "open source repository", "url": "https://github.com/VLSIDA/OpenRAM", "use": "Reference for SRAM compiler block organization and module boundaries.", "rights_note": "BSD-3-Clause source; do not copy implementation into lesson text." }, { "source_id": "MEM17-S03", "title": "OpenRAM architecture documentation", "source_type": "official documentation", "url": "https://github.com/VLSIDA/OpenRAM/blob/stable/docs/source/architecture.md", "use": "Confirms per-port blocks including address decoder wordline driver column mux precharge sense amplifier write driver and replica/control logic.", "rights_note": "Paraphrase; link-first citation." }, { "source_id": "MEM17-S04", "title": "OpenRAM column_mux.py", "source_type": "open source code", "url": "https://github.com/VLSIDA/OpenRAM/blob/stable/compiler/modules/column_mux.py", "use": "Reference for a single column mux cell using two pass devices controlled by a select signal.", "rights_note": "Do not copy source code; extract educational concept only." }, { "source_id": "MEM17-S05", "title": "OpenRAM column_mux_array.py", "source_type": "open source code", "url": "https://github.com/VLSIDA/OpenRAM/blob/stable/compiler/modules/column_mux_array.py", "use": "Reference for tiling column mux cells and deriving words_per_row from columns over word_size.", "rights_note": "Do not copy source code." }, { "source_id": "MEM17-S06", "title": "OpenRAM write_driver_array.py", "source_type": "open source code", "url": "https://github.com/VLSIDA/OpenRAM/blob/stable/compiler/modules/write_driver_array.py", "use": "Reference for write drivers organized per output bit and connected through the column path.", "rights_note": "Do not copy source code." }, { "source_id": "MEM17-S07", "title": "OpenRAM sense_amp.py", "source_type": "open source code", "url": "https://github.com/VLSIDA/OpenRAM/blob/stable/compiler/modules/sense_amp.py", "use": "Reference for sense amplifier as a distinct column-interface module.", "rights_note": "Do not copy source code." }, { "source_id": "MEM17-S08", "title": "OpenRAM: An Open-Source Memory Compiler", "source_type": "paper", "url": "https://escholarship.org/content/qt8x19c778/qt8x19c778_noSplash_b2b3fbbb57f1269f86d0de77865b0691.pdf", "use": "Architecture context for column mux sense amplifier write driver and control logic in an open SRAM compiler.", "rights_note": "Use citation and original summary only." }, { "source_id": "MEM17-S09", "title": "OpenRAM: An Open-Source Memory Compiler thesis", "source_type": "thesis", "url": "https://escholarship.org/content/qt2vv5q88z/qt2vv5q88z_noSplash_389063a5d89db05d7b42a63b528c7fc2.pdf", "use": "Background on early OpenRAM block placement and write-driver/column-mux routing context.", "rights_note": "Use citation and original summary only." }, { "source_id": "MEM17-S10", "title": "Timing Characterization of an SRAM Generated from OpenRAM", "source_type": "public report", "url": "https://scispace.com/pdf/timing-characterization-of-an-sram-generated-from-openram-an-13sjzt0bil.pdf", "use": "Public educational context for bidirectional column mux between bitlines and sense/write paths.", "rights_note": "Use as contextual pointer only; no figure copying." }, { "source_id": "MEM17-S11", "title": "CACTI 7 download page", "source_type": "official tool page", "url": "https://users.cs.utah.edu/~rajeev/cacti7/", "use": "Reference for memory analytical models spanning decoder sense amplifier cell latch and I/O tradeoffs.", "rights_note": "Paraphrase public tool description." }, { "source_id": "MEM17-S12", "title": "CACTI 5.1 technical report", "source_type": "technical report", "url": "https://shiftleft.com/mirrors/www.hpl.hp.com/techreports/2008/HPL-2008-20.html", "use": "High-level memory timing power area modeling context for caches and memories.", "rights_note": "Use bibliographic facts and original summary only." }, { "source_id": "MEM17-S13", "title": "CACTI-IO technical report", "source_type": "technical report", "url": "https://vlsicad.ucsd.edu/Publications/Reports/CS2012-0986.pdf", "use": "Separates on-chip SRAM column I/O from off-chip PHY modeling and provides I/O modeling boundary language.", "rights_note": "Use citation and original summary only." }, { "source_id": "MEM17-S14", "title": "Ngspice simulator and documentation", "source_type": "open tool documentation", "url": "https://ngspice.sourceforge.io/", "use": "Reproducible PDK-free transient simulation backend.", "rights_note": "Tool citation only." }, { "source_id": "MEM17-S15", "title": "OpenRAM FSiC 2019 slides", "source_type": "public slide deck", "url": "https://wiki.f-si.org/images/d/df/OpenRAM_FSiC2019.pdf", "use": "Public high-level confirmation of OpenRAM generated SRAM blocks including column mux sense amps and write drivers.", "rights_note": "No slide or figure copying." }, { "source_id": "MEM17-S16", "title": "SA-MEM-013 bitline precharge fixture", "source_type": "project artifact", "url": "../07_assets/memory_lab/experiments/SA_MEM_013_PRECHARGE_EQUALIZATION_V1/", "use": "Project-owned continuity for local bitline precharge/equalization before column selection.", "rights_note": "Project-owned generated artifact." }, { "source_id": "MEM17-S17", "title": "SA-MEM-014 write driver fixture", "source_type": "project artifact", "url": "../07_assets/memory_lab/experiments/SA_MEM_014_WRITE_DRIVER_V1/", "use": "Project-owned continuity for write-driver strength and read/write path boundary.", "rights_note": "Project-owned generated artifact." }, { "source_id": "MEM17-S18", "title": "SA-MEM-015 sense amplifier fixture", "source_type": "project artifact", "url": "../07_assets/memory_lab/experiments/SA_MEM_015_SENSE_AMPLIFIER_V1/", "use": "Project-owned continuity for sense input differential timing and load sensitivity.", "rights_note": "Project-owned generated artifact." }, { "source_id": "MEM17-S19", "title": "SA-MEM-016 row/wordline fixture", "source_type": "project artifact", "url": "../07_assets/memory_lab/experiments/SA_MEM_016_ROW_DECODER_WORDLINE_DRIVER_V1/", "use": "Project-owned continuity for row path launching bitline development before column I/O.", "rights_note": "Project-owned generated artifact." }, { "source_id": "MEM17-S20", "title": "SRAM master learning path", "source_type": "project roadmap", "url": "../00_admin/SRAM_MASTER_LEARNING_PATH_2026-07-24.md", "use": "Defines Chapter 4 item 22 as Column MUX and SRAM I/O.", "rights_note": "Project-owned roadmap artifact." } ], "public_boundary": [ "Precomputed educational data only.", "No live server solver execution.", "No arbitrary netlist, PDK, private model, or uploaded design ingestion.", "No account, payment, comment, newsletter action, job submission, or service intake workflow.", "No macro timing, yield, reliability, foundry, silicon, or product signoff claim." ] }