{
  "schema": "semiagora.sram-controller.v1",
  "title": "8x8 synchronous SRAM controller verified transaction trace",
  "protocol": {
    "accept": "req && ready at rising edge",
    "latency_cycles": 1,
    "completion": "rvalid pulse for reads and writes",
    "read_data": "valid with rvalid after a read"
  },
  "tools": {
    "iverilog": "12.0",
    "verilator": "5.020"
  },
  "verification": {
    "testbench": "pass",
    "assertion_failures": 0,
    "verilator_lint": "pass",
    "checked_responses": 7
  },
  "trace": [
    {
      "cycle": 1,
      "rst_n": 0,
      "req": 0,
      "ready": 1,
      "write": 0,
      "addr": 0,
      "wdata": 0,
      "rvalid": 0,
      "rdata": 0
    },
    {
      "cycle": 2,
      "rst_n": 0,
      "req": 0,
      "ready": 1,
      "write": 0,
      "addr": 0,
      "wdata": 0,
      "rvalid": 0,
      "rdata": 0
    },
    {
      "cycle": 3,
      "rst_n": 1,
      "req": 1,
      "ready": 0,
      "write": 1,
      "addr": 3,
      "wdata": 90,
      "rvalid": 0,
      "rdata": 0
    },
    {
      "cycle": 4,
      "rst_n": 1,
      "req": 0,
      "ready": 1,
      "write": 1,
      "addr": 3,
      "wdata": 90,
      "rvalid": 1,
      "rdata": 0
    },
    {
      "cycle": 5,
      "rst_n": 1,
      "req": 1,
      "ready": 0,
      "write": 0,
      "addr": 3,
      "wdata": 0,
      "rvalid": 0,
      "rdata": 0
    },
    {
      "cycle": 6,
      "rst_n": 1,
      "req": 0,
      "ready": 1,
      "write": 0,
      "addr": 3,
      "wdata": 0,
      "rvalid": 1,
      "rdata": 90
    },
    {
      "cycle": 7,
      "rst_n": 1,
      "req": 1,
      "ready": 0,
      "write": 1,
      "addr": 6,
      "wdata": 195,
      "rvalid": 0,
      "rdata": 90
    },
    {
      "cycle": 8,
      "rst_n": 1,
      "req": 0,
      "ready": 1,
      "write": 1,
      "addr": 6,
      "wdata": 195,
      "rvalid": 1,
      "rdata": 90
    },
    {
      "cycle": 9,
      "rst_n": 1,
      "req": 1,
      "ready": 0,
      "write": 0,
      "addr": 6,
      "wdata": 0,
      "rvalid": 0,
      "rdata": 90
    },
    {
      "cycle": 10,
      "rst_n": 1,
      "req": 0,
      "ready": 1,
      "write": 0,
      "addr": 6,
      "wdata": 0,
      "rvalid": 1,
      "rdata": 195
    },
    {
      "cycle": 11,
      "rst_n": 1,
      "req": 1,
      "ready": 0,
      "write": 0,
      "addr": 1,
      "wdata": 0,
      "rvalid": 0,
      "rdata": 195
    },
    {
      "cycle": 12,
      "rst_n": 1,
      "req": 0,
      "ready": 1,
      "write": 0,
      "addr": 1,
      "wdata": 0,
      "rvalid": 1,
      "rdata": 0
    },
    {
      "cycle": 13,
      "rst_n": 1,
      "req": 1,
      "ready": 0,
      "write": 1,
      "addr": 3,
      "wdata": 165,
      "rvalid": 0,
      "rdata": 0
    },
    {
      "cycle": 14,
      "rst_n": 1,
      "req": 0,
      "ready": 1,
      "write": 1,
      "addr": 3,
      "wdata": 165,
      "rvalid": 1,
      "rdata": 0
    },
    {
      "cycle": 15,
      "rst_n": 1,
      "req": 1,
      "ready": 0,
      "write": 0,
      "addr": 3,
      "wdata": 0,
      "rvalid": 0,
      "rdata": 0
    },
    {
      "cycle": 16,
      "rst_n": 1,
      "req": 0,
      "ready": 1,
      "write": 0,
      "addr": 3,
      "wdata": 0,
      "rvalid": 1,
      "rdata": 165
    },
    {
      "cycle": 17,
      "rst_n": 1,
      "req": 0,
      "ready": 1,
      "write": 0,
      "addr": 3,
      "wdata": 0,
      "rvalid": 0,
      "rdata": 165
    },
    {
      "cycle": 18,
      "rst_n": 1,
      "req": 0,
      "ready": 1,
      "write": 0,
      "addr": 3,
      "wdata": 0,
      "rvalid": 0,
      "rdata": 165
    }
  ],
  "transactions": [
    {
      "op": "WRITE",
      "addr": 3,
      "data": 90
    },
    {
      "op": "READ",
      "addr": 3,
      "expect": 90
    },
    {
      "op": "WRITE",
      "addr": 6,
      "data": 195
    },
    {
      "op": "READ",
      "addr": 6,
      "expect": 195
    },
    {
      "op": "READ",
      "addr": 1,
      "expect": 0
    },
    {
      "op": "WRITE",
      "addr": 3,
      "data": 165
    },
    {
      "op": "READ",
      "addr": 3,
      "expect": 165
    }
  ],
  "sha256": {
    "rtl/sram_controller.sv": "a2f0c0c22122d24ce1c1995898370892aa899a1259a69751f6674812a4b1edb9",
    "tb/sram_controller_tb.sv": "993e6d41a78f1f63a6f8ec552ddf6ef1573b0a765ef9c4e8ce8b969fc36da518"
  },
  "limitations": [
    "Educational inferred-register SRAM, not a foundry memory macro.",
    "The browser replays verified preset traces and never executes arbitrary user HDL.",
    "Analog timing, setup/hold, metastability, PVT, and physical memory effects are outside this RTL model."
  ]
}