`timescale 1ns/1ps
module sram_controller #(parameter int ADDR_W=3, parameter int DATA_W=8)(input logic clk,input logic rst_n,input logic req,input logic write,input logic [ADDR_W-1:0] addr,input logic [DATA_W-1:0] wdata,output logic ready,output logic rvalid,output logic [DATA_W-1:0] rdata);
  typedef enum logic {IDLE,EXECUTE} state_t; state_t state;
  logic latched_write; logic [ADDR_W-1:0] latched_addr; logic [DATA_W-1:0] latched_wdata;
  logic [DATA_W-1:0] memory [0:(1<<ADDR_W)-1]; integer index;
  assign ready=(state==IDLE);
  always_ff @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin state<=IDLE;rvalid<=0;rdata<='0;latched_write<=0;latched_addr<='0;latched_wdata<='0;for(index=0;index<(1<<ADDR_W);index=index+1)memory[index]<='0;end
    else begin rvalid<=0;case(state)
      IDLE:if(req)begin latched_write<=write;latched_addr<=addr;latched_wdata<=wdata;state<=EXECUTE;end
      EXECUTE:begin if(latched_write)memory[latched_addr]<=latched_wdata;else rdata<=memory[latched_addr];rvalid<=1;state<=IDLE;end
    endcase end
  end
endmodule