# SA-EDA-STDCELL-001 - Standard-Cell Report Literacy Replay

Version: 2026-08-22-v87

## Purpose

This browser CSV replay teaches how a designer reads standard-cell delay, drive strength, input slew, output load, pin capacitance, area, leakage, setup slack, hold slack, max-cap/max-slew pressure, and report stage together. It is an educational report-literacy model, not a replacement for a real library or timing tool.

## Dataset

- Rows: 3456
- Cell archetypes: 6
- Drive strengths: 4
- Input slew bins: 3
- Output load bins: 4
- Report stages: 4
- Optimization goals: 3
- Live server runs: 0

## Method

1. Assign normalized synthetic proxies for a small set of common standard-cell archetypes and drive-strength labels.
2. Sweep input slew, output load, report stage, and optimization goal.
3. Estimate report-literacy metrics for delay, output slew, capacitance pressure, setup/hold slack proxies, area/power pressure, evidence state, and decision gate.
4. Keep the source spine link-only and never copy Liberty tables, standard-cell files, OpenROAD reports, command transcripts, PDK files, or signoff data.

## Public Boundary

- No Liberty table, standard-cell library, LEF/DEF/GDS/SPEF/SDC, OpenROAD report body, command transcript, or PDK/rule deck is copied.
- No live OpenROAD, OpenLane, OpenSTA, Yosys, ABC, PEX, SPICE, or server-side EDA execution is active.
- No uploaded design, uploaded report, timing-closure claim, tapeout claim, product claim, foundry claim, or signoff authority is enabled.

## Replacement Evidence Needed

Real engineering reuse would need owned RTL/netlist, library files, constraints, parasitic extraction, tool versions, timing reports, area/power reports, signoff policy, and design-owner review.