# v64 Deep Semiconductor Simulation Model Card

Generated from `DEEP_SEMICONDUCTOR_V64_2026-08-14`.

This package adds precomputed educational simulations for PVD step coverage,
FO4 timing, DRAM charge sharing, DRAM retention, RowHammer risk, NAND threshold
margin, FeFET hysteresis, HBM thermal bandwidth, memory hierarchy placement,
FinFET PPA, GAA nanosheet electrostatics, and plasma etch UQ.

## Public Boundary

- No live server solver execution.
- No PDK, proprietary compact model, measured silicon, equipment recipe, chamber
  condition, process instruction, qualification signoff, upload, account,
  payment, comment, newsletter signup, or job/event submission workflow.
- Third-party tools remain source links until license, dependency, and model
  boundaries are reviewed.

## Intended Use

Use these cards for concept learning, paper planning, route design, methods
notes, and evidence triage. Do not cite them as calibrated process data,
measured devices, memory-controller results, equipment instructions, or product
release evidence.