Explain why a CMOS inverter transfer curve is analog even when the circuit is used as a digital gate.
Checked against the linked simulation evidence rather than a hidden slide-only claim.
LESSON PACKET / SA-CIR-001
An analog curve becomes
a digital gate.
Use the CMOS inverter as the first circuit lesson spine: static transfer, gain, propagation delay, feedback, and evidence boundaries in one packet.
LEARNING OUTCOMES
What the learner should be able to defend.
This packet is designed so a student can follow the lesson, while a researcher can jump straight into the simulation objects and reuse the evidence with the limits attached.
Identify VM, gain, VIL, VIH, NML, and NMH from the published VTC evidence.
Checked against the linked simulation evidence rather than a hidden slide-only claim.
Connect capacitive loading to propagation delay through the ring-oscillator extraction identity.
Checked against the linked simulation evidence rather than a hidden slide-only claim.
Separate precomputed educational evidence from signoff timing, PVT, and silicon claims.
Checked against the linked simulation evidence rather than a hidden slide-only claim.
LECTURE ARC
From transfer curve to clock.
The lesson begins with a DC curve, extracts the digital meaning of gain and margins, then moves into transient delay and a feedback loop that exposes frequency.
A rail-to-rail curve restores logic.
The inverter is not a magic Boolean object. It is two MOS devices exchanging current as VIN moves from 0 V to VDD.
A steep analog region creates digital tolerance.
The sampled slope exposes the high-gain region, while the -1 crossings bound the input ranges treated as valid low and high.
A load turns switching into time.
The output node must charge or discharge capacitance before the next gate sees a changed logic state.
An odd loop makes delay measurable.
A ring oscillator converts repeated inverter delay into a period and frequency that can be extracted from a saved transient waveform.
SIMULATION BUNDLE
The lecture is not the only entry point.
Paper writers may need only the simulation package. These entries are first-class catalog objects with Explore, Run Card, Export, Methods, Limits, and Evidence sections.
CMOS inverter VTC and gain
Sweep VIN, plot VOUT, estimate switching point, sampled gain, and noise margins.
Open simulation ->CMOS inverter propagation delay
Use ring-oscillator transients to extract per-stage delay across stage count and load.
Open simulation ->Ring oscillator frequency
Close an odd inversion loop and turn inverter delay into a measurable oscillation frequency.
Open simulation ->EVIDENCE PACK
Use the plots with the files that made them.
The current MVP exposes saved datasets, netlists, and source notes. It does not accept uploaded circuits or launch live SPICE jobs from the public site.
VM = 0.87 V / |gain|max = 11.90
DC VTC and sampled gain from the SKY130 inverter evidence package.
Open VTC simulation ->td = 62.4 ps representative case
Per-stage delay extracted from the 3-stage, 5 fF ring-oscillator transient case.
Open delay simulation ->f = 2.671 GHz representative case
Frequency extracted from saved VDD/2 crossings after startup.
Open ring simulation ->REVIEW GATE
Do not promote a draft video as final.
The web lesson can be published as a review packet while the final media stays gated. This avoids confusing a script/PPT review artifact with an approved lecture video.
SA-CIR-001 packet assembled
This page is the public web packet for the CMOS inverter lecture arc.
Review pending
The v03 approval gate has not been marked complete here, so no final video is presented or linked.
Precomputed evidence live
The three circuit simulations are browseable with datasets, netlists, methods, limits, and evidence notes.
Publication boundary
Review pending means the lecture page is usable for structure and simulation access, but the v03 approval gate must be completed before any final video label appears.