Body effect
The threshold-voltage shift caused by a voltage difference between a MOSFET source and body.
- It changes drive strength and leakage when device terminals are not at the same potential.
- /learn#device-path
- /resources#lab-directory
SEMIAGORA GLOSSARY
Define the word.
Expose the boundary.
Short semiconductor definitions tied to reproduced labs and evidence pages. The goal is not a dictionary dump; it is a shared vocabulary for reading conditions, models, and claims correctly.
TERM INDEX
Start by layer, not alphabet.
Device, circuit, memory, layout, verification, and research terms are separated because the same word can carry different assumptions at different model levels.
Device
Device terms.
4 entries in this layer.
BSIM
A family of compact MOSFET models used by circuit simulators to represent foundry-calibrated transistor behavior.
- It is the bridge between device physics and practical SPICE circuit prediction.
- /resources#lab-directory
- /research/simulation-map
DIBL
Drain-induced barrier lowering, where the drain voltage reduces the source-channel barrier in a short-channel MOSFET.
- It increases off-current and weakens gate control in scaled devices.
- /learn#device-path
- /resources#education
Threshold voltage
A practical extraction point for MOSFET turn-on, not a single universal physical switch.
- Different extraction methods and bias conditions can produce different threshold numbers.
- /labs/mosfet-transfer
- /learn#device-path
Circuit
Circuit terms.
5 entries in this layer.
Capacitance
The charge stored per volt between conductors or terminals.
- It turns voltage changes into delay, dynamic energy, coupling noise, and memory retention limits.
- /labs/mos-capacitor-cv
- /labs/interconnect-delay
- /labs/dram-retention
Corner
A named process and model condition such as TT, SS, or FF used to approximate manufacturing variation.
- A result at one corner is not a full PVT characterization.
- /labs/cmos-inverter
- /labs/ring-oscillator
gm
MOSFET transconductance, the small-signal change in drain current per change in gate voltage.
- It links device bias to gain, speed, and analog sensitivity.
- /labs/mosfet-transfer
- /learn#circuit-path
Noise margin
The voltage tolerance between valid logic levels and the switching thresholds that separate them.
- It explains why a transistor circuit can restore digital values despite analog imperfections.
- /labs/cmos-inverter
- /learn#circuit-path
Propagation delay
The time between an input transition and the corresponding output transition at a defined threshold.
- It turns device current and capacitance into digital speed.
- /labs/ring-oscillator
- /labs/interconnect-delay
Memory
Memory terms.
8 entries in this layer.
Access transistor
The SRAM pass device that connects an internal storage node to a bitline when the wordline is asserted.
- It must be strong enough to read and write, but not so strong that a read destroys the stored state.
- /labs/sram-read
- /labs/sram-snm
- /labs/sram-write-boundary
Bitline pair
The complementary BL and BLB wires that carry small read differentials and forced write values in an SRAM column.
- Bitline capacitance controls sensing delay, energy, and write difficulty.
- /labs/sram-read
- /labs/bitline-sensing
Precharge
The operation that initializes bitlines to a known voltage before a memory read or write phase.
- It sets the starting condition for differential sensing and memory timing.
- /labs/sram-read
- /learn#memory-path
Read disturb
The internal-node voltage movement caused by reading a stored SRAM value.
- A read operation must expose the state without flipping it.
- /labs/sram-read
- /labs/sram-snm
Retention time
The time a dynamic storage node can keep enough voltage margin before refresh or sensing fails.
- It converts leakage physics into a controller deadline.
- /labs/dram-retention
Sense amplifier
A circuit that converts a small bitline voltage difference into a full digital value.
- Its enable timing is constrained by cell current, bitline capacitance, offset, and noise.
- /labs/bitline-sensing
- /learn#memory-path
Static noise margin
The DC voltage margin of a bistable memory cell, often visualized with a butterfly plot.
- It separates latch stability from dynamic write or sensing success.
- /labs/sram-snm
- /labs/sram-write-boundary
Wordline
The SRAM row-control signal that turns on access transistors for selected cells.
- Wordline amplitude and timing affect read disturb, write success, and cell access speed.
- /labs/sram-read
- /labs/sram-write-boundary
Layout
Layout terms.
4 entries in this layer.
DRC
Design rule checking, the geometric verification that layout shapes satisfy process constraints.
- A schematic can be logically correct while the drawn layout is not manufacturable.
- /labs/physical-verification
GDSII
A standard layout file format that stores mask geometry for integrated-circuit designs.
- It is the artifact that physical-verification tools inspect before tapeout.
- /labs/physical-verification
- /resources#open-silicon
LVS
Layout versus schematic checking, which compares extracted layout connectivity against the intended circuit.
- It proves that the drawn shapes implement the intended devices and nets.
- /labs/physical-verification
PDK
A process design kit containing rules, models, cells, and technology data for a manufacturing process.
- PDK access and license boundaries determine what can be simulated, published, or redistributed.
- /resources#open-silicon
- /terms
Verification
Verification terms.
0 entries in this layer.
Research
Research terms.
3 entries in this layer.
Compact model
A computationally efficient model used by circuit simulators to approximate device terminal behavior.
- Compact models are useful and calibrated, but their boundaries must be stated with process, corner, voltage, and temperature.
- /research/simulation-map
- /resources#lab-directory
SPICE
A circuit-simulation method and netlist style used to solve circuit behavior from models and sources.
- SPICE evidence is reproducible only when models, conditions, netlists, and extraction rules are preserved.
- /labs
- /research/simulation-map
Workflow boundary
The stated limit separating executed evidence from indexed references, illustrative examples, or future work.
- It prevents a learning site from implying that a result was measured, simulated, or verified when it was not.
- /research
- /corrections
- /terms