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SASemiAgoraSemiconductor knowledge & engineeringEvidence catalog

SIMULATION IMPLEMENTATION ATLAS

One model.
One honest interaction.

A working map from semiconductor question to engine, browser experience, evidence package, and the boundary that must remain visible.

01

Execute first.

The browser replays or explores a verified result. It never presents an invented curve as simulation evidence.

02

Match the interaction.

Bias sweeps need cursors, transient circuits need waveforms, digital protocols need cycle traces, and physical flows need artifact gates.

03

Expose the boundary.

Engine, model fidelity, conditions, verification, downloads, provenance, and known omissions travel with every result.

LIVE / EXECUTED

Twenty-three implementations,
five interaction patterns.

DOMAINSIMULATIONENGINEWEB IMPLEMENTATIONOPEN
DEVICEPN junctionDEVSIMbias slider + field profilesRun ->
DEVICE2D MOSFET transferDEVSIMbias sweep + surface carriersRun ->
DEVICEMOS capacitor C-VDEVSIMbias cursor + C-V mode + carriersRun ->
CIRCUITCMOS inverter VTCngspice + SKY130DC cursor + noise marginsRun ->
CIRCUITRing oscillatorngspice + SKY130stage/load matrix + waveformRun ->
MEMORY6T SRAM readngspice + SKY130load sweep + disturb traceRun ->
MEMORY6T SRAM SNMngspicebutterfly + margin extractionRun ->
MEMORYSRAM write boundaryngspice + SKY130assist shmoo + waveform replayRun ->
MEMORYSRAM memory depthSemiAgora modelsense margin + disturb + assist + cache evidenceRun ->
LAYOUTInterconnect crosstalkngspicecoupling selector + victim peakRun ->
LAYOUTPower rail IR dropngspiceload selector + rail gradientRun ->
LAYOUTDistributed interconnectngspicesection selector + Elmore comparisonRun ->
MEMORYBitline sensingngspicecell-current cases + enable thresholdRun ->
MEMORYDRAM retentionngspiceleakage cases + refresh markerRun ->
LAYOUTPhysical verificationMagic / Netgen / ngspiceGDS -> DRC -> LVS -> PEX -> delayRun ->
PROCESSSurface treatmentSemiAgora modelO2 plasma + O3 ozone evidence cardsRun ->
PROCESSThermal processingSemiAgora modelRTA + thermal budget + TED + silicide cardsRun ->
PROCESSWet clean surface prepSemiAgora modelwet clean + native oxide + HMDS + sequence cardsRun ->
EQUIPMENTEquipment and facilitiesSemiAgora equipment facilities modelcleanroom + vacuum + tool state + utilities cardsRun ->
PACKAGINGPackaging, test, reliabilitySemiAgora PTR modelpackage parasitics + thermal + sort + reliability cardsRun ->
DIGITALSRAM controllerIcarus + Verilatorcycle scrubber + protocol stateRun ->
DIGITALMarch C- BISTIcarus + Verilatorfault scenario + 80-cycle replayRun ->
DIGITALSECDED ECCIcarus + Verilatorbit injection + decoder verdictRun ->
PARAMETER SWEEPslider -> nearest executed condition -> metrics + curvePN, MOSFET, inverter, oscillator, SRAM read
TRACE REPLAYscenario -> cycle -> state + expected/observedcontroller, BIST, ECC
PHYSICAL PIPELINEartifact -> verification gate -> extracted consequenceDRC, LVS, PEX, timing
DYNAMIC BOUNDARYshmoo cell -> pass/fail verdict -> waveform replaySRAM write-success boundary
MARGIN EXTRACTIONcurve intersection -> threshold -> safe/unsafe regionSNM and DRAM retention

IMPLEMENTATION QUEUE

What comes next,
and how it should appear.

These are scoped candidates, not simulated claims. Promotion to Live requires an executed dataset, invariant tests, downloadable source, and a declared model boundary.

EXPAND

OpenRAM macro

OpenRAM / word width / depth / corner

macro browser + timing/power table

GATE: large toolchain and PDK dependencies
EXPAND

RTL-to-GDS peripheral

OpenLane 2 / OpenROAD / clock / utilization / constraints

floorplan + timing + area evidence

GATE: queued offline execution
EXPAND

Cache behavior

gem5 / cache size / associativity / workload

miss-rate and latency comparison

GATE: architecture abstraction and run cost
OPTIONAL

Interactive logic editor

DigitalJS / OpenCircuits / netlist / stimulus

editable decoder and controller

GATE: sandbox and license boundary
OPTIONAL

VHDL memory controller

GHDL / generic parameters / test vectors

trace replay + assertions

GATE: isolated compile service

SOURCE STRATEGY

Reuse engines.
Own the evidence contract.

WaveDrom, DEVSIM, DigitalJS, CircuitJS1, ngspice, OpenRAM, OpenCircuits, Verilator, GHDL, OpenLane 2, OpenROAD, and gem5 are cataloged separately by license, execution mode, adoption status, and integration risk.

Inspect sources and licenses ->