Skip to content
SASemiAgoraSemiconductor knowledgeResearch services
Menu
Research services한국어 안내LearnTraceCompareReproducePlanSearch
ExploreKnowledge AtlasDetailed mapSimulationsDomain mapGuided journeysLabs
WorkspacesScenario ComparisonReproducibility RegistryExperiment PlannerResearch Project BuilderClaim-Evidence WorkbenchData Contract
TrustEvidence Knowledge GraphMetric OntologyCitation ProvenanceSource WorkspaceEvidence BrowserPublic Release LedgerSource PolicyCorrections
MoreSearchPracticeCalculatorsResourcesResearch atlasRelease provenanceReading RoomResearch servicesAbout SemiAgora
SASemiAgoraSemiconductor knowledge & engineeringStart with sense margin

MEMORY REPLAY LAB / SA-MEM-DEPTH-001

Replay the SRAM stack.
Do not mix the claims.

This lab is a compact surface for five promoted memory-depth simulations. It keeps peripheral margin, column I/O, bitcell stability, assist tradeoff, and cache behavior visible as separate evidence layers.

Sense Margin11 / 12Column MUX/I/O864Read Disturb10 / 12Assist Taxonomy5Cache Replay1.52-68 cycles

REPLAY CARDS

One knob family at a time.

Open each run card for exports, methods, limits, and evidence. The lab itself stays static so the public site can scale to many memory simulations without enabling risky workflows.

SA-MEM-DEPTH-SENSE-001

SRAM sense amplifier decision margin

Replay bitline differential, offset sigma, attenuation loss, positive margin, and decision-time interpretation before claiming a sense amplifier can resolve.

  • Compare bitline differential against a 3-sigma offset budget before reading timing.
  • Notice that unsafe cases do not receive a decision-time number.
  • Use attenuation loss to keep peripheral loading visible in the claim.
Open run card ->
SA-MEM-017

SRAM column MUX and I/O interactive replay

A browser CSV replay of 864 verified PDK-free ngspice cases connecting mux ratio, pass-device scale, shared sense/I/O load, write-path off-state, transfer efficiency, and output latency.

  • Filter mux ratio and shared sense/I/O load to see why a wider words-per-row mux can trade area for latency and input attenuation.
  • Compare clean and leaky write-path off-state rows to separate read-mode loading from write-driver function.
  • Watch transfer efficiency, shared differential, common-mode, unselected disturbance, and output latency as separate observables.
  • Use the source catalog and model card before reusing any row in a paper note or slide.
Open run card ->
SA-MEM-DEPTH-READ-DISTURB-001

SRAM read-disturb sizing

Replay how normalized cell ratio and wordline pulse width change read-disturb peak, read-SNM proxy, and a retained/not-retained budget.

  • Raise the cell-ratio proxy and inspect how the disturb budget improves.
  • Lengthen the wordline pulse and watch dynamic disturb worsen.
  • Keep read-SNM proxy separate from the dynamic disturb peak.
Open run card ->
SA-MEM-DEPTH-ASSIST-001

SRAM assist taxonomy

Classify baseline write, cell-VDD collapse, wordline boost, negative bitline, and read wordline-underdrive as tradeoff cards instead of recipe settings.

  • Compare which assist helps write margin and which protects read stability.
  • Read energy index and coupling risk before treating margin gain as free.
  • Use the taxonomy to name evidence needed for a real assist decision.
Open run card ->
SA-MEM-DEPTH-CACHE-001

Cache behavior replay for SRAM latency intuition

Replay blocked, sequential, strided, random, and conflict-thrashing access patterns with AMAT so SRAM timing stays connected to system-visible latency.

  • Compare blocked access against random pointer walking.
  • Read miss rate and miss penalty before interpreting AMAT.
  • Keep architecture-visible latency separate from bitcell or sense-amplifier timing.
Open run card ->

EXPORT BUNDLE

Datasets before conclusions.

Every promoted replay ships a JSON dataset, a shared model script, a model card, source anchors, and explicit limits. PDK files, private traces, and signoff material are not distributed.

Sense Margin

Downloads

  • Dataset JSON: /data/sram-sense-amplifier-decision-margin-web-v1.json
  • Model script: /data/sram_memory_depth_models.mjs
  • Model card: /data/sram-memory-depth-model-card.md
Open dataset ->
Column MUX/I/O

Downloads

  • Interactive CSV rows: /data/sram-column-mux-io-v75.csv
  • Web result JSON: /data/sram-column-mux-io-web-v1.json
  • Source catalog CSV: /data/sram-column-mux-io-source-catalog-v1.csv
  • Model card: /data/sram-column-mux-io-model-card-v1.md
Open dataset ->
Read Disturb

Downloads

  • Dataset JSON: /data/sram-read-disturb-sizing-web-v1.json
  • Model script: /data/sram_memory_depth_models.mjs
  • Model card: /data/sram-memory-depth-model-card.md
Open dataset ->
Assist Taxonomy

Downloads

  • Dataset JSON: /data/sram-assist-taxonomy-web-v1.json
  • Model script: /data/sram_memory_depth_models.mjs
  • Model card: /data/sram-memory-depth-model-card.md
Open dataset ->
Cache Replay

Downloads

  • Dataset JSON: /data/sram-cache-behavior-replay-web-v1.json
  • Model script: /data/sram_memory_depth_models.mjs
  • Model card: /data/sram-memory-depth-model-card.md
Open dataset ->

Lab boundary

No arbitrary SPICE, arbitrary HDL, upload, account, ATE programming, qualification signoff, product release, or live server execution is enabled. This is a reading and replay lab for memory evidence discipline.

Open lesson packet ->