Memory learning path
Concept sequence and review gate.
Open route ->DOMAIN LANE / MEMORY
Memory
SRAM / DRAM / memory test / architecture
How does memory preserve, sense, move, disturb, retain, protect, and place data across SRAM, DRAM, HBM, NAND, MRAM, FeFET, SCM, CIM, and hybrid memory systems?
ROUTE STACK
Start with the right surface.
This lane collects the learning packets, replay labs, simulation objects, and evidence routes that belong together. It is a filter, not a new workflow engine.
SRAM write-boundary lab
Browser replay or visual evidence surface.
Open route ->DRAM retention lab
Browser replay or visual evidence surface.
Open route ->SRAM SECDED ECC fault replay
Typed precomputed object with methods, limits, and exports.
Open route ->SRAM memory-depth lesson
Concept sequence and review gate.
Open route ->SRAM memory-depth replay lab
Browser replay or visual evidence surface.
Open route ->SRAM sense amplifier decision margin
Typed precomputed object with methods, limits, and exports.
Open route ->SRAM read-disturb sizing
Typed precomputed object with methods, limits, and exports.
Open route ->SRAM assist taxonomy
Typed precomputed object with methods, limits, and exports.
Open route ->Cache behavior replay for SRAM latency intuition
Typed precomputed object with methods, limits, and exports.
Open route ->SRAM read lab
Browser replay or visual evidence surface.
Open route ->SRAM stability lab
Browser replay or visual evidence surface.
Open route ->Bitline sensing lab
Browser replay or visual evidence surface.
Open route ->SRAM controller lab
Browser replay or visual evidence surface.
Open route ->SRAM BIST lab
Browser replay or visual evidence surface.
Open route ->SRAM ECC lab
Browser replay or visual evidence surface.
Open route ->SRAM read transient and bitline delay
Typed precomputed object with methods, limits, and exports.
Open route ->SRAM static noise margin butterfly
Typed precomputed object with methods, limits, and exports.
Open route ->SRAM write-boundary simulation
Typed precomputed object with methods, limits, and exports.
Open route ->SRAM bitline differential sensing
Typed precomputed object with methods, limits, and exports.
Open route ->SRAM controller protocol trace
Typed precomputed object with methods, limits, and exports.
Open route ->March C- SRAM BIST fault replay
Typed precomputed object with methods, limits, and exports.
Open route ->DRAM, HBM, and emerging memory lesson
Concept sequence and review gate.
Open route ->DRAM, HBM, and emerging memory replay lab
Browser replay or visual evidence surface.
Open route ->DRAM/HBM row-buffer and bank parallelism
Typed precomputed object with methods, limits, and exports.
Open route ->MRAM switching energy versus retention
Typed precomputed object with methods, limits, and exports.
Open route ->RRAM, PCM, and FeFET read-margin degradation
Typed precomputed object with methods, limits, and exports.
Open route ->CIM crossbar accuracy and energy tradeoff
Typed precomputed object with methods, limits, and exports.
Open route ->DRAM 1T1C charge sharing and sense margin
Typed precomputed object with methods, limits, and exports.
Open route ->DRAM retention tail and refresh policy
Typed precomputed object with methods, limits, and exports.
Open route ->DRAM RowHammer disturb and ECC risk
Typed precomputed object with methods, limits, and exports.
Open route ->NAND threshold distributions and ECC margin
Typed precomputed object with methods, limits, and exports.
Open route ->FeFET hysteresis, wake-up, fatigue, and usable window
Typed precomputed object with methods, limits, and exports.
Open route ->HBM thermal bandwidth roofline
Typed precomputed object with methods, limits, and exports.
Open route ->Memory hierarchy placement map
Typed precomputed object with methods, limits, and exports.
Open route ->MRAM fundamentals lesson
Concept sequence and review gate.
Open route ->MRAM fundamentals replay lab
Browser replay or visual evidence surface.
Open route ->MRAM switching/read/retention triangle
Typed precomputed object with methods, limits, and exports.
Open route ->PCM SET/RESET pulse and resistance-drift replay
Typed precomputed object with methods, limits, and exports.
Open route ->ReRAM set/reset variability and read-window replay
Typed precomputed object with methods, limits, and exports.
Open route ->3D NAND string Vt distribution, read-retry, and ECC margin replay
Typed precomputed object with methods, limits, and exports.
Open route ->SRAM column MUX and I/O lesson
Concept sequence and review gate.
Open route ->SRAM column MUX and I/O replay lab
Browser replay or visual evidence surface.
Open route ->SRAM column MUX and I/O interactive replay
Typed precomputed object with methods, limits, and exports.
Open route ->HBM/base-die partition lesson
Concept sequence and review gate.
Open route ->HBM/base-die partition replay lab
Browser replay or visual evidence surface.
Open route ->HBM/base-die partition map
Typed precomputed object with methods, limits, and exports.
Open route ->DRAM refresh, RowHammer, and ECC guardband lesson
Concept sequence and review gate.
Open route ->DRAM refresh, RowHammer, and ECC guardband replay lab
Browser replay or visual evidence surface.
Open route ->DRAM refresh, RowHammer, and ECC guardband replay
Typed precomputed object with methods, limits, and exports.
Open route ->Emerging memory placement and reliability lesson
Concept sequence and review gate.
Open route ->Emerging memory placement and reliability replay lab
Browser replay or visual evidence surface.
Open route ->Emerging memory placement and reliability map
Typed precomputed object with methods, limits, and exports.
Open route ->learn/m3d igo sram integration evidence
Concept sequence and review gate.
Open route ->labs/m3d igo sram integration evidence
Browser replay or visual evidence surface.
Open route ->Monolithic-3D Si/oxide-semiconductor SRAM integration evidence ladder
Typed precomputed object with methods, limits, and exports.
Open route ->learn/process device yield integration
Concept sequence and review gate.
Open route ->labs/process device yield integration
Browser replay or visual evidence surface.
Open route ->Process-device-yield integration evidence map
Typed precomputed object with methods, limits, and exports.
Open route ->SIMULATION FILTER
The existing catalog, narrowed to this domain.
Paper-writing users can enter from this page and open the relevant run cards, exports, methods, limits, and evidence without first watching a lecture.
SRAM read transient and bitline delay
Replay SKY130 6T read cases across bitline load, 100 mV sense delay, and internal-node disturb.
56.6-247.7 ps30 / 100 / 300 fF<0.182 V
Open run card ->SRAM static noise margin butterfly
Compare hold and read butterfly curves, maximum-square SNM, and read-access margin loss.
449 mV279 mV37.9%
Open run card ->SRAM write-boundary simulation
Replay the 24-case SKY130 shmoo that maps dynamic write success versus wordline level and write-VDD assist.
24 transients18 pass / 6 fail1.2 -> 1.0 V WL
Open run card ->SRAM bitline differential sensing
Replay a lumped-bitline model that connects cell current, bitline capacitance, and sense-enable timing.
500 -> 125 ps20 / 40 / 80 uA100 mV
Open run card ->SRAM sense amplifier decision margin
Replay bitline differential, offset sigma, attenuation loss, positive margin, and decision-time interpretation before claiming a sense amplifier can resolve.
11 / 127 mV111.1-332.9 ps
Open run card ->SRAM read-disturb sizing
Replay how normalized cell ratio and wordline pulse width change read-disturb peak, read-SNM proxy, and a retained/not-retained budget.
10 / 12187 mV224.7 mV
Open run card ->SRAM assist taxonomy
Classify baseline write, cell-VDD collapse, wordline boost, negative bitline, and read wordline-underdrive as tradeoff cards instead of recipe settings.
5118 mV64 mV
Open run card ->Cache behavior replay for SRAM latency intuition
Replay blocked, sequential, strided, random, and conflict-thrashing access patterns with AMAT so SRAM timing stays connected to system-visible latency.
1.52-68 cycles527.37x
Open run card ->SRAM controller protocol trace
Replay the verified transaction trace that turns read/write requests into one-cycle checked responses.
7 / 7 checked18 cycles0 failures
Open run card ->March C- SRAM BIST fault replay
Replay 80-access March C- traces for no-fault, stuck-at-0, and stuck-at-1 SRAM scenarios.
240 total80 accesses0 / 2 / 3
Open run card ->SRAM SECDED ECC fault replay
Replay exhaustive one- and two-bit codeword fault injection for an 8-bit SECDED memory word.
92 injections13 / 13 corrected78 / 78 detected
Open run card ->DRAM/HBM row-buffer and bank parallelism
Replay row-hit rate and bank count to see why locality and bank-level parallelism shape DRAM/HBM latency and throughput before raw bandwidth matters.
1.606x32 banks / 90% hits12 cases
Open run card ->MRAM switching energy versus retention
Replay STT/SOT-style write probability, pulse width, retention barrier, and write energy as a compact MRAM tradeoff card.
35.35 fJSOT / 40 kT / 0.5 ns24 cases
Open run card ->RRAM, PCM, and FeFET read-margin degradation
Replay endurance, temperature, variability, and normalized read margin across RRAM, PCM, and FeFET style memory labels.
866878 ppmPCM / 100k cycles / 125 C27 cases
Open run card ->CIM crossbar accuracy and energy tradeoff
Replay array size, ADC bits, conductance variation, accuracy proxy, and energy index for compute-in-memory crossbar intuition.
0.12299564 array / 4-bit ADC / 3% sigma27 cases
Open run card ->DRAM 1T1C charge sharing and sense margin
Replay cell capacitance, bitline capacitance, and stored voltage to see the small differential a DRAM sense amplifier must resolve.
126.56535 fF cell / 80 fF BL / 0.95 V18 cases
Open run card ->DRAM retention tail and refresh policy
Replay leakage class, temperature, and refresh interval to see why weak-cell tails drive refresh policy.
1072000tail / 105 C / 64 ms48 cases
Open run card ->DRAM RowHammer disturb and ECC risk
Replay activation count, victim distance, and temperature to frame RowHammer as a pattern, margin, mitigation, and ECC-evidence problem.
112673.08250k ACT / distance 1 / 85 C24 cases
Open run card ->NAND threshold distributions and ECC margin
Replay SLC/MLC/TLC/QLC threshold crowding, P/E cycles, retention time, and ECC margin proxy.
0.01TLC / 100 P-E / 36 months36 cases
Open run card ->FeFET hysteresis, wake-up, fatigue, and usable window
Replay cycle count, temperature, and program pulse to see how ferroelectric memory window can wake up, fatigue, and shift.
441.6100000 cycles / 25 C / 3 V16 cases
Open run card ->HBM thermal bandwidth roofline
Replay stack height, target bandwidth, and cooling class to see usable bandwidth, energy per bit, and throttle risk together.
0.31864-high / 1.6 TB/s / enhanced18 cases
Open run card ->Memory hierarchy placement map
Replay SRAM, DRAM, HBM, SCM, NAND, and MRAM across workload weights to choose the right evidence question.
0.76206SRAM / edge always-on24 cases
Open run card ->MRAM switching/read/retention triangle
Replay STT/SOT labels, thermal barrier, and pulse width to compare write energy, switch probability, read margin, retention, and disturb risk.
1.2758SOT / 80 kT / 0.5 ns18 cases
Open run card ->PCM SET/RESET pulse and resistance-drift replay
Replay SET/RESET pulse proxies, retention time, drift coefficient, and read margin so PCM is taught as a window-and-drift problem, not one ideal resistance ratio.
223.588 mV10054 cases
Open run card ->ReRAM set/reset variability and read-window replay
Replay compliance, cycling, temperature, selector on/off ratio, and LRS/HRS spread to see why ReRAM is a variability and array-read problem.
164.612 mV41.241%54 cases
Open run card ->3D NAND string Vt distribution, read-retry, and ECC margin replay
Replay layer group, program/erase cycles, retention time, and read-retry steps to connect 3D NAND stack variation with threshold overlap and ECC margin.
16.82 dB-6.14 dB108 cases
Open run card ->SRAM column MUX and I/O interactive replay
A browser CSV replay of 864 verified PDK-free ngspice cases connecting mux ratio, pass-device scale, shared sense/I/O load, write-path off-state, transfer efficiency, and output latency.
864423 to 546 ps503
Open run card ->HBM/base-die partition map
A browser CSV lab for memory-system partitioning: compare workload traffic, HBM stack class, base-die controller/PHY/RAS placement, interposer budget, thermal class, capacity, bandwidth, energy, and yield risk before calling an HBM plan feasible.
1296 cases4 strategies0
Open run card ->DRAM refresh, RowHammer, and ECC guardband replay
A browser CSV replay that keeps temperature, retention-tail cells, refresh policy, activation pressure, RowHammer disturbance risk, ECC coverage, thermal stress, and next evidence check in one table.
409640
Open run card ->Emerging memory placement and reliability map
A browser CSV replay that compares SRAM, DRAM, HBM, NAND, MRAM, FeFET, ReRAM, PCM, SCM, embedded NVM, and CIM-style memory across placement, reliability, integration, and evidence maturity.
1728120
Open run card ->Monolithic-3D Si/oxide-semiconductor SRAM integration evidence ladder
Trace declared device tiers and oxide-semiconductor access transport through contacts, inter-tier connectivity, WL/BL loading, thermal budget, extraction maturity, cell/subarray sensitivities, contradictions, and owned replacement evidence without copying a topology or issuing a node, architecture, or signoff claim.
614490
Open run card ->Process-device-yield integration evidence map
Follow bounded process variation families through device characterization, circuit margin, reliability and yield observations, three exact ledgers, four accountable role views, upstream packet postures, and a human-reviewed public-atlas gate without claiming physical causality, signoff, qualification, or production fitness.
576028800
Open run card ->DEEPENING PLAN
From concept to research artifact.
Memory depth now spans SRAM cell/peripheral/I/O, DRAM/HBM locality, HBM/base-die partitioning, DRAM 1T1C sensing, retention, refresh, RowHammer, ECC/scrub guardbands, NAND threshold margin, MRAM switching/read/retention, FeFET/FeRAM, PCM, ReRAM, CIM, SCM, eDRAM/MIMCAP, 3D memory, and hierarchy placement while keeping device, cell, peripheral, controller, package, system, reliability, and evidence layers separate.
Vocabulary and mechanisms
- Cell-state ladder: hold, read, disturb, write, and retention.
- Peripheral ladder: precharge, wordline, bitline, sense, write driver, and assist.
- System ladder: controller trace, BIST fault model, ECC syndrome, and cache-level implication.
Queued seed simulations
- Sense-amplifier decision replay with bitline differential, offset proxy, and decision time.
- Read-disturb sizing replay connecting SNM, cell ratio, and wordline pulse.
- Write-assist taxonomy replay separating VDD collapse, wordline boost, and negative bitline vocabulary.
- Cache behavior replay linking SRAM latency and miss policy to system-level timing.
- Column-mux and SRAM I/O replay connecting local bitline differential, shared sense/I/O load, write-path off-state, transfer efficiency, and output timing.
- HBM/base-die partition map connecting workload traffic, controller/PHY/RAS placement, TSV/interposer pressure, thermal headroom, bandwidth, capacity, and yield risk.
- DRAM refresh, RowHammer, ECC, temperature, retention-tail, thermal, and guardband replay connecting weak-tail cells to controller/system evidence.
- Emerging memory placement and reliability map comparing SRAM, DRAM, HBM, NAND, eDRAM/MIMCAP, MRAM, FeFET/FeRAM, ReRAM, PCM, SCM/CXL memory, embedded NVM, and CIM-style memory.
- M3D Si/oxide-semiconductor SRAM evidence ladder from tier and access-device declarations through contacts, inter-tier links, WL/BL loading, thermal and extraction maturity, cell/subarray sensitivities, contradictions, and replacement gates.
- Process-device-yield integration replay separating variation families, device evidence, circuit margin, reliability and yield evidence, genealogy, role review, exact ledgers, and the human-reviewed public-atlas handoff.
Claim fitness checks
- Analog timing plot and digital protocol trace are kept as separate evidence artifacts.
- Every memory margin states whether it is static, dynamic, pre-layout, or measured.
- Fault and ECC examples state the modeled fault universe before claiming coverage.
- Column-interface evidence must state mux ratio, selected bitline depth, pass-device scale, shared load, write off-state, common-mode, and output extraction rule.
- HBM partition evidence card with operator, engineer, integration, and yield views before any bandwidth or capacity claim is reused.
- DRAM reliability rows must state retention tail, temperature, access activation pressure, refresh policy, protection policy, ECC/scrub evidence, residual risk, and next safe check.
- Emerging memory rows must state placement target, integration context, workload, decision priority, endurance, retention, read-margin, thermal/process, integration risk, evidence maturity, and next safe check.
- An M3D SRAM claim must retain topology/conditions, device and compact-model lineage, contacts, inter-tier connectivity, thermal budget, layout/PEX, cell/subarray read-write evidence, variation, uncertainty, and accountable review.
- Operational attribution requires owned process and equipment history, calibrated metrology, device characterization and models, circuit context, reliability and test evidence, lot-wafer-die-device genealogy, uncertainty, validation, and accountable human approval.
Paper-ready artifacts
- One cell-level margin table with operating condition.
- One peripheral timing diagram with signal ownership.
- One system trace showing how a memory event reaches architecture-visible behavior.
- One column-interface table separating local differential, shared differential, transfer efficiency, common-mode, output timing, and non-claims.
- One DRAM reliability guardband table separating retention-tail, refresh-tax, RowHammer, ECC/scrub, thermal, and product-boundary evidence.
- One emerging-memory taxonomy table separating placement shortlist from integration, endurance, retention, read-margin, thermal/process, and poor-fit review states.
- One nine-node claim map spanning oxide interfaces, thermal budget, contacts, interconnect, SRAM read/write/subarray evidence, and RC extraction.
Capstone Target
A memory evidence packet now travels from SRAM cell/peripheral/I/O evidence into DRAM/HBM locality, MRAM switching, RRAM/PCM/FeFET margin, CIM crossbar tradeoffs, controller traces, BIST, and ECC without blurring abstraction layers.
Open all-domain roadmap ->EVIDENCE BACKLOG
What this lane needs next.
The backlog keeps future additions useful rather than noisy. New pages should enter through a domain tag, public source anchor, model boundary, and precomputed evidence package.
What is already usable
- The memory lane now spans twelve SRAM objects plus DRAM/HBM locality, 1T1C sensing, retention, refresh/ECC guardbands, RowHammer, NAND, 3D NAND, PCM, ReRAM, FeFET/FeRAM, MRAM switching/read/retention, SCM, eDRAM/MIMCAP, hierarchy, placement, and CIM cards.
- Read, stability, write, bitline, column mux/I/O, sense margin, disturb, assist, cache, controller, BIST, ECC, retention, Flash margin, 3D NAND Vt/ECC, PCM drift, ReRAM variability, HBM roofline, HBM/base-die partitioning, MRAM triangle, and hierarchy evidence are grouped as one lane.
- Twenty-three memory-depth and memory-expansion seeds have been promoted into real precomputed or browser-interactive simulation objects, including the v81 HBM/base-die partition map, v85 DRAM guardband replay, and v86 emerging-memory placement map.
Good candidates
- SRAM column decoder and bank I/O handoff
- compiler-style aspect ratio and words-per-row tradeoff
- measured DRAM retention, syndrome, scrub, and thermal replacement data
- measured replacement evidence for MRAM, FeFET, ReRAM, PCM, NAND, DRAM, HBM, and SCM placement claims
- owned M3D SRAM topology/conditions, compact-model lineage, contacts, inter-tier connectivity, thermal budget, cell/subarray stability, timing, energy, variation, uncertainty, and review evidence
- owned process, device, circuit, reliability, test, genealogy, yield, uncertainty, and accountable review evidence for cross-domain attribution
BOUNDARIES
Useful domain content, no hidden operations.
Every domain can grow as education, simulation replay, and evidence planning. The page must not become a job board, tool controller, recipe workflow, upload service, or signoff surface.
pre-layout teaching results unless stated
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
protocol evidence is not analog timing
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no copied SRAM topology, dimensions, source parasitics, node claim, architecture ranking, product comparison, or signoff
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no automatic causal attribution, equipment action, model calibration, circuit signoff, reliability qualification, product binning, wafer disposition, yield decision, or publication action
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
SOURCE SPINE
Anchors for vocabulary and scope.
These source links help name the domain. They do not convert teaching replays into certified measurements, process recipes, facility procedures, or product signoff results.
UCLA eScholarship SRAM sense amplifier thesis
Public thesis used for offset, attenuation, control-timing, and sense-amplifier vocabulary.
Open source ->Grossar et al. SRAM read stability and write-ability
Public paper used for read-stability, write-ability, SNM, and N-curve vocabulary.
Open source ->NVIDIA reverse write assist and SRAM VMIN paper
Public paper used to anchor assist, reverse assist, VMIN, guardband, and canary vocabulary.
Open source ->CS61C average memory access time notes
Public course note used for hit time, miss rate, miss penalty, and AMAT vocabulary.
Open source ->Ramulator2
External MIT-licensed DRAM/HBM memory-system simulator reference; SemiAgora page uses original precomputed teaching data.
Open source ->DRAMsim3
External MIT-licensed DRAM timing and thermal-capable simulator reference.
Open source ->DNN+NeuroSim V2.1
External compute-in-memory accelerator reference; link-only until license and model boundaries are reviewed.
Open source ->MNSIM 2.0
External memristor PIM behavior-level simulator reference; link-only until manual rights review.
Open source ->NEIGHBOR DOMAINS
Move sideways without returning home.
Semiconductor work is coupled. These links keep the site navigable when one claim crosses process, device, circuit, memory, equipment, metrology, or reliability boundaries.
Process
What changed on the wafer, and what evidence proves it?
Open domain ->Device
How do charge, potential, materials, thermal path, and carriers become I-V, C-V, RF, or power-device evidence?
Open domain ->Circuit
How does a device-level curve become gain, delay, and oscillation?
Open domain ->Digital / Verification
What cycle-level contract was actually checked?
Open domain ->EDA / Layout
How do layout markers, connectivity reports, parasitics, and timing evidence become a public-safe verification claim?
Open domain ->Equipment / Facilities
What tool or facility condition supports the process, and what is still not an operating instruction?
Open domain ->Metrology / Yield
Is the measurement fit for the claim?
Open domain ->Packaging / Test / Reliability
What evidence remains after the die is fabricated, bonded, packaged, screened, and stressed?
Open domain ->