1.606xBest throughput indexUNKNOWNInspect metric contract
32 banks / 90% hitsBest caseUNKNOWNInspect metric contract
12 casesSweep rowsUNKNOWNInspect metric contract
SIMULATION / SA-SEED-MEM-DRAM-HBM-BANK-001
DRAM/HBM row-buffer and bank parallelism
DRAM/HBM Bank
Replay row-hit rate and bank count to see why locality and bank-level parallelism shape DRAM/HBM latency and throughput before raw bandwidth matters.
EXPLORE
Start with the observable.
Use this page when the simulation is the primary artifact. The linked lesson explains the concept; the linked lab keeps the visual replay surface available.
- Compare row-hit rate before assuming more banks alone solve memory latency.
- Read average latency and throughput index together so locality and parallelism stay coupled.
- Use the result as a bridge to Ramulator2 or DRAMsim3, not as a DRAM-standard timing claim.
RUN CARD
Conditions before conclusions.
This page replays saved DRAM/HBM surrogate data and does not run a live memory-system simulator.
Primary knobs
- Bank count
- Row-hit rate
- Nominal hit/miss cycle model
Saved outputs
- Average latency proxy
- Throughput index
- Best-case summary
EXPORT
Download the public artifacts.
These exports are the supported public files for review. PDK files and restricted third-party material are not redistributed.
Dataset JSON
/data/dram-hbm-row-buffer-bank-parallelism-web-v1.json
Open file ->Seed sweep summary CSV
/data/github-open-source-seed-sweep-summary.csv
Open file ->Seed model script
/data/github_open_source_seed_sims.py
Open file ->Seed model card
/data/github-open-source-seed-sims-model-card.md
Open file ->METHODS
How the number was made.
Methods are written for citation discipline: the extraction rule matters as much as the plotted value.
Average hit and miss cycles are blended by row-hit rate and adjusted by a bank-conflict proxy.
Keep this method attached when reusing the figure or metric.
Throughput index combines bank count, efficiency, and average cycle cost.
Keep this method attached when reusing the figure or metric.
The row-hit and bank axes are intentionally normalized for classroom comparison.
Keep this method attached when reusing the figure or metric.
LIMITS
What this page does not claim.
The MVP is useful because the limits are visible. These statements prevent a teaching simulation from being cited as silicon evidence.
Not a cycle-accurate DRAM, HBM, controller, refresh, thermal, or RowHammer model.
Carry this boundary into any derivative note, paper draft, or slide.
No JEDEC timing table, commercial memory configuration, or measured trace is included.
Carry this boundary into any derivative note, paper draft, or slide.
Research-grade studies should use Ramulator2, DRAMsim3, or measured traces after setup review.
Carry this boundary into any derivative note, paper draft, or slide.
EVIDENCE
Trace the claim back to artifacts.
The evidence route remains the catalog-level browser; this page is the simulation-level reading card.
Seed sweep JSON records every row and the best throughput-index case.
SA-SEED-MEM-DRAM-HBM-BANK-001
CSV export preserves the row-hit, bank-count, latency, and throughput columns.
SA-SEED-MEM-DRAM-HBM-BANK-001
GitHub expedition note records Ramulator2 and DRAMsim3 as external solver references.
SA-SEED-MEM-DRAM-HBM-BANK-001
Source spine
These links anchor the public teaching model. They do not convert the replay into a qualified process recipe or signoff result.
Public execution boundary
No server-side live ngspice execution, uploads, accounts, payments, comments, newsletter signup, or job/event submissions are active on this page.