Locality and banks come before bandwidth slogans.
Row-buffer hit rate and bank-level parallelism shape latency and throughput before the architecture can benefit from raw interface bandwidth.
32 banks / 90% hits / open ->LESSON PACKET / SA-MEM-002
Memory beyond SRAM.
Keep the hierarchy visible.
This packet expands the memory lane into DRAM/HBM behavior, HBM/base-die partitioning, DRAM reliability guardbands, DRAM 1T1C sensing, retention, refresh/ECC guardbands, RowHammer, NAND, 3D NAND, PCM drift, ReRAM variability, FeFET, MRAM switching, hierarchy placement, and CIM crossbar tradeoffs while keeping every page precomputed and source-bounded.
MEMORY EXPANSION
The site should not feel SRAM-only.
SRAM remains one deep spine, but a semiconductor memory school also needs volatile memory, retention, disturbance, Flash, ferroelectric devices, hierarchy placement, and compute-near-memory vocabulary.
Retention and write energy pull against each other.
A useful MRAM note keeps barrier, pulse width, current, switch probability, and energy together before comparing STT and SOT categories.
35.35 fJ / open ->Read margin is a distribution question.
RRAM, PCM, and FeFET labels are not enough. Endurance, temperature, variability, and margin degradation decide whether a read remains useful.
27 cases / open ->Compute-in-memory is an analog tradeoff surface.
Array size, ADC bits, conductance variation, IR drop, and energy must be visible before a CIM accuracy claim becomes meaningful.
64 / 4-bit / 3% / open ->Charge sharing creates the first tiny sense signal.
Cell capacitance, bitline capacitance, and stored voltage determine the differential that the sense amplifier must turn into a full logic state.
126.565 mV / open ->Refresh policy is controlled by the weak-cell tail.
Temperature, leakage class, and refresh interval trade bandwidth tax against the probability that the tail of the array fails first.
tail / 105 C / open ->Activation patterns can become reliability and security evidence.
RowHammer must separate activation count, victim distance, temperature, margin, mitigation, and ECC residual-risk language.
24 cases / open ->Retention, refresh, RowHammer, ECC, and thermal pressure belong in one table.
The v85 replay links weak-tail cells, temperature, refresh tax, activation pressure, protection policy, residual uncorrectable-risk proxy, thermal stress, and next evidence check.
4096 rows / open ->More bits per cell crowd the threshold distributions.
SLC, MLC, TLC, and QLC trade density against P/E cycling, retention drift, read overlap, and ECC margin.
SLC to QLC / open ->FeFET memory window needs wake-up, fatigue, and imprint context.
A single hysteresis width is not enough. Cycle count, temperature, and program-pulse proxy define the usable read window.
441.6 mV / open ->Bandwidth is only useful inside a thermal roofline.
Stack height, target bandwidth, cooling class, power, energy per bit, and throttle risk decide the usable bandwidth.
thermal roofline / open ->Base-die partitioning moves controller, PHY, RAS, and interface tradeoffs into the package question.
The v81 map compares host-controller, base-die controller, controller/PHY/RAS, and custom die-to-die wrapper partitions against TSV, interposer, thermal, capacity, bandwidth, integration, and yield-risk proxies.
1296 rows / open ->The best memory depends on the workload question.
SRAM, DRAM, HBM, SCM, NAND, and MRAM should be compared by latency, bandwidth, capacity, endurance, and energy movement.
6 technologies / open ->Resistance drift turns a fresh window into a future read problem.
SET/RESET pulse proxies, temperature, retention time, and spread decide whether a phase-change memory state remains readable after aging.
54 cases / open ->A clean HRS/LRS label is not enough.
Compliance, cycling, temperature, and selector on/off ratio shape the usable read window before ReRAM can be compared as an array technology.
54 cases / open ->Layer variation and retention reach the ECC budget.
Layer group, P/E cycles, retention days, and read-retry steps connect stack-level threshold spread to a system-facing ECC margin.
108 cases / open ->Placement target decides what an emerging memory claim means.
The v86 replay compares SRAM, DRAM, HBM, NAND, MRAM, FeFET, ReRAM, PCM, SCM, embedded NVM, eDRAM, and CIM-style memory across placement, reliability, integration, workload, and evidence maturity.
1728 rows / open ->SIMULATION BUNDLE
Start from the run card if you are writing.
Each object keeps Explore, Run Card, Export, Methods, Limits, and Evidence. The lesson explains the stack; the simulation page carries the artifact.
DRAM/HBM row-buffer and bank parallelism
Replay row-hit rate and bank count to see why locality and bank-level parallelism shape DRAM/HBM latency and throughput before raw bandwidth matters.
1.606x32 banks / 90% hits12 cases
Open simulation ->MRAM switching energy versus retention
Replay STT/SOT-style write probability, pulse width, retention barrier, and write energy as a compact MRAM tradeoff card.
35.35 fJSOT / 40 kT / 0.5 ns24 cases
Open simulation ->RRAM, PCM, and FeFET read-margin degradation
Replay endurance, temperature, variability, and normalized read margin across RRAM, PCM, and FeFET style memory labels.
866878 ppmPCM / 100k cycles / 125 C27 cases
Open simulation ->CIM crossbar accuracy and energy tradeoff
Replay array size, ADC bits, conductance variation, accuracy proxy, and energy index for compute-in-memory crossbar intuition.
0.12299564 array / 4-bit ADC / 3% sigma27 cases
Open simulation ->DRAM 1T1C charge sharing and sense margin
Replay cell capacitance, bitline capacitance, and stored voltage to see the small differential a DRAM sense amplifier must resolve.
126.56535 fF cell / 80 fF BL / 0.95 V18 cases
Open simulation ->DRAM retention tail and refresh policy
Replay leakage class, temperature, and refresh interval to see why weak-cell tails drive refresh policy.
1072000tail / 105 C / 64 ms48 cases
Open simulation ->DRAM RowHammer disturb and ECC risk
Replay activation count, victim distance, and temperature to frame RowHammer as a pattern, margin, mitigation, and ECC-evidence problem.
112673.08250k ACT / distance 1 / 85 C24 cases
Open simulation ->NAND threshold distributions and ECC margin
Replay SLC/MLC/TLC/QLC threshold crowding, P/E cycles, retention time, and ECC margin proxy.
0.01TLC / 100 P-E / 36 months36 cases
Open simulation ->FeFET hysteresis, wake-up, fatigue, and usable window
Replay cycle count, temperature, and program pulse to see how ferroelectric memory window can wake up, fatigue, and shift.
441.6100000 cycles / 25 C / 3 V16 cases
Open simulation ->HBM thermal bandwidth roofline
Replay stack height, target bandwidth, and cooling class to see usable bandwidth, energy per bit, and throttle risk together.
0.31864-high / 1.6 TB/s / enhanced18 cases
Open simulation ->Memory hierarchy placement map
Replay SRAM, DRAM, HBM, SCM, NAND, and MRAM across workload weights to choose the right evidence question.
0.76206SRAM / edge always-on24 cases
Open simulation ->PCM SET/RESET pulse and resistance-drift replay
Replay SET/RESET pulse proxies, retention time, drift coefficient, and read margin so PCM is taught as a window-and-drift problem, not one ideal resistance ratio.
223.588 mV10054 cases
Open simulation ->ReRAM set/reset variability and read-window replay
Replay compliance, cycling, temperature, selector on/off ratio, and LRS/HRS spread to see why ReRAM is a variability and array-read problem.
164.612 mV41.241%54 cases
Open simulation ->3D NAND string Vt distribution, read-retry, and ECC margin replay
Replay layer group, program/erase cycles, retention time, and read-retry steps to connect 3D NAND stack variation with threshold overlap and ECC margin.
16.82 dB-6.14 dB108 cases
Open simulation ->SOURCE SPINE
Study the tools without copying them.
Ramulator2 and DRAMsim3 are strong local-build candidates. NeuroSim, MNSIM, CrossSim, and Flash or FeFET device references stay link-only until license and model boundaries are reviewed.
Ramulator2
https://github.com/CMU-SAFARI/ramulator2
Open source ->DRAMsim3
https://github.com/umd-memsys/DRAMsim3
Open source ->Micron HBM overview
https://www.micron.com/products/memory/hbm
Open source ->Semiconductor Engineering custom HBM
https://semiengineering.com/how-will-the-custom-hbm-business-work/
Open source ->Purdue Semiconductor Memory 101
https://engineering.purdue.edu/online/semiconductors/semiconductor-memory-101
Open source ->Google Security Rowhammer research support
https://blog.google/security/supporting-rowhammer-research-to/
Open source ->imec active memory overview
https://www.imec-int.com/en/expertise/cmos-advanced/store/memory
Open source ->InMRAM introductory course metadata
https://arxiv.org/abs/1906.10206
Open source ->DNN+NeuroSim V2.1
https://github.com/neurosim/DNN_NeuroSim_V2.1
Open source ->MNSIM 2.0
https://github.com/thu-nics/MNSIM-2.0
Open source ->CrossSim
https://github.com/sandialabs/cross-sim
Open source ->Public boundary
No live memory-system simulator, micromagnetic solver, material compact model, neural-network workload, DRAM controller test, Flash ECC service, upload, account, payment, comment, newsletter signup, or product signoff workflow is active. These are precomputed teaching replays.
Open Memory domain ->