REPLAY CARDS
Different memories, different evidence.
Each card has a downloadable dataset, source spine, methods, limits, and public execution boundary. It is built for study and paper planning, not qualification, controller testing, or product ranking.
SA-SEED-MEM-DRAM-HBM-BANK-001DRAM/HBM row-buffer and bank parallelism
Replay row-hit rate and bank count to see why locality and bank-level parallelism shape DRAM/HBM latency and throughput before raw bandwidth matters.
- Compare row-hit rate before assuming more banks alone solve memory latency.
- Read average latency and throughput index together so locality and parallelism stay coupled.
- Use the result as a bridge to Ramulator2 or DRAMsim3, not as a DRAM-standard timing claim.
Open run card ->SA-SEED-MEM-MRAM-SWITCH-001MRAM switching energy versus retention
Replay STT/SOT-style write probability, pulse width, retention barrier, and write energy as a compact MRAM tradeoff card.
- Move retention barrier and pulse width together to see why write energy is not independent.
- Compare STT and SOT labels as architecture cues, not as calibrated stack predictions.
- Use switch probability as a lesson proxy before studying micromagnetics or silicon data.
Open run card ->SA-SEED-MEM-ENVM-MARGIN-001RRAM, PCM, and FeFET read-margin degradation
Replay endurance, temperature, variability, and normalized read margin across RRAM, PCM, and FeFET style memory labels.
- Treat emerging memory as a margin distribution problem rather than a single technology label.
- Compare endurance and temperature before ranking RRAM, PCM, or FeFET.
- Use the worst-case proxy to ask what metrology or compact model would replace this toy model.
Open run card ->SA-SEED-MEM-CIM-CROSSBAR-001CIM crossbar accuracy and energy tradeoff
Replay array size, ADC bits, conductance variation, accuracy proxy, and energy index for compute-in-memory crossbar intuition.
- Compare array size, ADC precision, and conductance variation instead of treating CIM as a single knob.
- Watch accuracy proxy and energy index move in opposite directions.
- Use the card to prepare for CrossSim, NeuroSim, or MNSIM study without copying those tools.
Open run card ->SA-MEM-003-DRAM-1T1C-SENSE-001DRAM 1T1C charge sharing and sense margin
Replay cell capacitance, bitline capacitance, and stored voltage to see the small differential a DRAM sense amplifier must resolve.
- Start from charge sharing before discussing DRAM timing names.
- Compare cell and bitline capacitance to see why the initial signal is tiny.
- Use sense margin and sense-time proxy as separate outputs.
Open run card ->SA-MEM-003-DRAM-RETENTION-REFRESH-001DRAM retention tail and refresh policy
Replay leakage class, temperature, and refresh interval to see why weak-cell tails drive refresh policy.
- Look at typical, weak, and tail leakage classes instead of one average cell.
- Trade refresh interval against bandwidth tax and fail-tail proxy.
- Use temperature acceleration as a prompt for real retention characterization.
Open run card ->SA-MEM-003-DRAM-ROWHAMMER-ECC-001DRAM RowHammer disturb and ECC risk
Replay activation count, victim distance, and temperature to frame RowHammer as a pattern, margin, mitigation, and ECC-evidence problem.
- Separate activation pattern, physical neighbor distance, temperature, and ECC residual risk.
- Use victim margin as the cell-level bridge before system mitigation language.
- Keep security, controller, and silicon evidence distinct.
Open run card ->SA-MEM-003-NAND-THRESHOLD-ECC-001NAND threshold distributions and ECC margin
Replay SLC/MLC/TLC/QLC threshold crowding, P/E cycles, retention time, and ECC margin proxy.
- Compare bits per cell before treating Flash as one memory technology.
- Read endurance and retention together because both widen threshold distributions.
- Use ECC margin as a system-facing translation of device distribution overlap.
Open run card ->SA-MEM-003-FEFET-HYSTERESIS-001FeFET hysteresis, wake-up, fatigue, and usable window
Replay cycle count, temperature, and program pulse to see how ferroelectric memory window can wake up, fatigue, and shift.
- Keep hysteresis window, imprint shift, wake-up, fatigue, and retention language together.
- Compare early-cycle and high-cycle behavior before trusting one memory-window number.
- Use the card to prepare for FeRAM/FeFET literature without copying device data.
Open run card ->SA-MEM-003-HBM-THERMAL-ROOFLINE-001HBM thermal bandwidth roofline
Replay stack height, target bandwidth, and cooling class to see usable bandwidth, energy per bit, and throttle risk together.
- Do not read HBM bandwidth without energy per bit and thermal headroom.
- Compare target bandwidth and usable bandwidth under throttle risk.
- Use stack height as a package/system knob, not just a capacity slogan.
Open run card ->SA-MEM-003-MEMORY-HIERARCHY-PLACEMENT-001Memory hierarchy placement map
Replay SRAM, DRAM, HBM, SCM, NAND, and MRAM across workload weights to choose the right evidence question.
- Pick the workload first, then compare memory technologies.
- Separate latency, bandwidth, capacity, endurance, and energy movement instead of asking for one best memory.
- Use the placement score as a discussion scaffold, not a product benchmark.
Open run card ->SA-MEM-PCM-001PCM SET/RESET pulse and resistance-drift replay
Replay SET/RESET pulse proxies, retention time, drift coefficient, and read margin so PCM is taught as a window-and-drift problem, not one ideal resistance ratio.
- Read PCM margin through fresh and aged resistance windows, not just a SET/RESET label.
- Move retention time and temperature together because drift turns a fresh window into a future read problem.
- Compare margin and risk side by side before using PCM in a memory-hierarchy note.
Open run card ->SA-MEM-RERAM-001ReRAM set/reset variability and read-window replay
Replay compliance, cycling, temperature, selector on/off ratio, and LRS/HRS spread to see why ReRAM is a variability and array-read problem.
- Treat HRS/LRS as distributions before treating ReRAM as a clean binary switch.
- Keep selector leakage and cycle count visible because array read margin can collapse before the ideal device story does.
- Use this as the deeper follow-up to the existing emerging-memory comparison card.
Open run card ->SA-MEM-NAND3D-0013D NAND string Vt distribution, read-retry, and ECC margin replay
Replay layer group, program/erase cycles, retention time, and read-retry steps to connect 3D NAND stack variation with threshold overlap and ECC margin.
- Move from generic NAND threshold crowding into layer-aware 3D NAND behavior.
- Keep retention, cycling, read-retry, and ECC in one table because storage reliability is a system chain.
- Use layer group as a public-safe way to discuss stack nonuniformity without vendor data.
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