126.565Largest sense marginUNKNOWNInspect metric contract
35 fF cell / 80 fF BL / 0.95 VBest caseUNKNOWNInspect metric contract
18 casesSweep rowsUNKNOWNInspect metric contract
SIMULATION / SA-MEM-003-DRAM-1T1C-SENSE-001
DRAM 1T1C charge sharing and sense margin
DRAM 1T1C Sense
Replay cell capacitance, bitline capacitance, and stored voltage to see the small differential a DRAM sense amplifier must resolve.
EXPLORE
Start with the observable.
Use this page when the simulation is the primary artifact. The linked lesson explains the concept; the linked lab keeps the visual replay surface available.
- Start from charge sharing before discussing DRAM timing names.
- Compare cell and bitline capacitance to see why the initial signal is tiny.
- Use sense margin and sense-time proxy as separate outputs.
RUN CARD
Conditions before conclusions.
This page replays saved DRAM 1T1C data and does not run a live DRAM circuit or proprietary memory macro.
Primary knobs
- Cell capacitance
- Bitline capacitance
- Stored cell voltage
Saved outputs
- Bitline delta
- Sense margin
- Sense-time proxy
EXPORT
Download the public artifacts.
These exports are the supported public files for review. PDK files and restricted third-party material are not redistributed.
Dataset JSON
/data/dram-1t1c-charge-sharing-sense-web-v1.json
Open file ->Dataset CSV
/data/dram-1t1c-charge-sharing-sense-v64.csv
Open file ->v64 deep simulation summary CSV
/data/v64-deep-simulations-summary.csv
Open file ->v64 deep model script
/data/v64_deep_semiconductor_sims.mjs
Open file ->v64 deep model card
/data/v64-deep-simulations-model-card.md
Open file ->METHODS
How the number was made.
Methods are written for citation discipline: the extraction rule matters as much as the plotted value.
Bitline delta is computed from a simple capacitive charge-sharing relation.
Keep this method attached when reusing the figure or metric.
Sense margin subtracts a fixed comparator/noise floor proxy from the bitline delta.
Keep this method attached when reusing the figure or metric.
Sense-time proxy falls as the available differential grows.
Keep this method attached when reusing the figure or metric.
LIMITS
What this page does not claim.
The MVP is useful because the limits are visible. These statements prevent a teaching simulation from being cited as silicon evidence.
No access transistor, parasitic network, bitline precharge circuit, sense-amplifier transistor model, or vendor DRAM timing is included.
Carry this boundary into any derivative note, paper draft, or slide.
No measured DRAM cell, JEDEC, retention, or product claim is made.
Carry this boundary into any derivative note, paper draft, or slide.
Use measured arrays or calibrated circuit models before citing DRAM sense margins.
Carry this boundary into any derivative note, paper draft, or slide.
EVIDENCE
Trace the claim back to artifacts.
The evidence route remains the catalog-level browser; this page is the simulation-level reading card.
v64 deep results store every capacitance, voltage, margin, and timing row.
SA-MEM-003-DRAM-1T1C-SENSE-001
CSV export preserves the charge-sharing table.
SA-MEM-003-DRAM-1T1C-SENSE-001
The memory lesson now separates 1T1C cell evidence from system-level DRAM/HBM behavior.
SA-MEM-003-DRAM-1T1C-SENSE-001
Source spine
These links anchor the public teaching model. They do not convert the replay into a qualified process recipe or signoff result.
Ramulator2External MIT-licensed DRAM/HBM simulator reference; v64 pages use original teaching data.DRAMsim3External MIT-licensed DRAM timing and thermal simulator reference.IEEE IRDSRoadmap source spine for memory hierarchy and emerging memory vocabulary.Google Security RowHammer research notePublic context for RowHammer as a DRAM charge-leakage, refresh, and security-evidence topic.
Public execution boundary
No server-side live ngspice execution, uploads, accounts, payments, comments, newsletter signup, or job/event submissions are active on this page.