CMOS Inverter: Analog Curve to Digital Gate
Explain VM, gain, VIL, VIH, NML, NMH, and why a DC curve cannot prove timing.
- syllabus
- notes
- simulation
- worksheet
- exam-style check
- evidence limits
STRUCTURED LEARNING
See the whole stack.
Master one causal chain.
Each path moves from a physical idea to an observable, a reproduced experiment, and the evidence behind the number.
THIRTY-NINE CONNECTED TRACKS
Choose a layer.
Keep the stack visible.
00EMFEATURED PATH
Emerging device, memory & integration
Seven technology topics across mechanism, integration, measurement, reliability, and product-readiness evidence, with held sources, open contradictions, and owned replacement slots kept visible
Inspect evidence maturity ->00DMFEATURED PATHDevice modeling & normalization
Geometry and effective width, total versus normalized Ioff, gm/Id operating conditions, synthetic TLM, contact drop, train/holdout residuals, corner versus Monte Carlo, and SPICE evidence layers
Lock the device contract ->00UQFEATURED PATHVariability, metrology & uncertainty
LER/LWR bandwidth, PSD and correlation, aperture filtering, sampling uncertainty, hierarchical variation, plasma-etch UQ, Gauge R&R, and hybrid-bonding metrology
Separate uncertainty ->01FEATURED PATHDevice physics
Carriers, bands, transport, junctions, and MOS electrostatics
Follow device path ->02NEW DEVICE PATHAdvanced devices
Planar MOSFET, FinFET, GAAFET, and CFET contextual comparison, CFET contact parasitics, GaN/SiC HEMT chain, dynamic Ron recovery, TCAD DOE/surrogate guardrails, variability, and PPA
Compare architecture ->02BV82 DEVICE PATHCFET contact parasitics
Stacked n/p devices, MOL contacts, vias, local interconnect, thermal coupling, delay, energy, and integration risk
Map CFET parasitics ->02CV83 POWER DEVICEGaN/SiC HEMT substrate chain
Semi-insulating SiC, GaN buffer traps, HEMT mode, thermal path, dynamic Ron, and reliability evidence
Trace GaN/SiC ->02DV88 POWER DEVICEGaN dynamic-Ron trap memory
Stress class, drain bias, recovery window, temperature, current collapse, measurement caution, and evidence gate
Read dynamic Ron ->02EV90 TCAD DOETCAD DOE and surrogate optimization
DOE plans, response surfaces, Gaussian-process uncertainty, extrapolation guards, mesh convergence, calibration anchors, and owner review
Guard optimizer evidence ->02FV91 DEVICE COMPARISONMOSFET to CFET architecture comparison
Electrostatic control, footprint, contacts, capacitance, variability, thermal coupling, integration risk, evidence maturity, and circuit handoff
Compare with context ->02GV99 PHOTONICSSemiconductor photonics & optoelectronics
Photon energy, bounded LED/laser logic, ideal detector responsivity, all-pass ring transfer, MZI phase modulation, and replacement evidence
Follow the photon ->02HV100 RFRF S-parameters & de-embedding
Complex two-port data, reference impedance, passive fixtures, correction assumptions, fT/fmax, RF noise, stability/passivity screens, and replacement evidence
Move the reference plane ->02IV101 CFET DTCO2D CFET contact-to-PPA evidence
Transport and contact hypotheses, local RC, extraction and compact-model maturity, circuit delay/energy/area proxies, contradictions, and owned replacement evidence
Carry the contact ->02JV102 SNSPDSuperconducting photon-detector evidence
Geometry, normalized current distribution, edge and constriction evidence, photon or dark context, mechanism ambiguity, timing and radiometry lineage, uncertainty, and replacement gates
Separate event evidence ->02KV103 M3D SRAMM3D Si/oxide-semiconductor SRAM evidence
Tier assignment, oxide access transport, contacts, inter-tier links, WL/BL loading, thermal budget, extraction maturity, cell/subarray sensitivities, contradictions, and replacement gates
Trace tier to subarray ->02LV104 NDR EVIDENCE2D heterojunction NDR evidence
Signed I-V, consecutive negative slope, rectification, peak/valley prominence, contact burden, sweep history, mechanism ambiguity, and replacement evidence
Test the NDR claim ->02MV105 SENSOR CALIBRATIONThermoelectric temperature-sensor evidence
Normalized response, series-junction scaling, reference-junction correction, drift, mechanical hysteresis, cross-sensitivity, uncertainty, traceability, and replacement evidence
Trace signal to evidence ->02NV106 PROCESS TOPOGRAPHYParticle Monte Carlo feature topography
Particle transport, surface interaction, reflection, secondary transport, exact conservation, evolving RIE/PVD profiles, role views, and replacement evidence
Follow transport to profile ->02OV107 PLASMA EQUIPMENTCCP and ICP chamber-state evidence
Source coupling, substrate bias, pressure, gas response, wall loss, matching, sheath, charged and neutral delivery, IEDF/IADF breadth, radial state, role gates, feature bridge, and replacement evidence
Separate chamber state ->02PV108 VACUUM EQUIPMENTVacuum and gas-delivery inventory evidence
Flow-model regime, gas admission, wall release, chamber and foreline inventory, conductance-limited pumping, settling, distribution, exact ledgers, role gates, and the bounded plasma handoff
Balance source and removal ->02QV109 RIE MECHANISMReactive-ion etch mechanism evidence
Surface family, ion drive, neutral reactivity, passivation, directionality, mask resilience, feature access, six mechanism regimes, exact ledgers, role gates, and bounded profile handoff
Separate the mechanism ->02RV110 INTEGRATIONProcess-device-yield integration evidence
Variation families, device characterization, circuit margin, reliability and yield context, genealogy, role review, exact ledgers, upstream packet postures, and a human-reviewed public-atlas gate
Trace the evidence chain ->02SV111 ETCH ATLASEtch depth and selectivity evidence atlas
HAR transport, ALE cycles, selective etch, DRIE passivation, strip and ash residue, wet-etch mass transfer, role gates, exact ledgers, and owned replacement evidence
Compare etch families ->02TV127 VARIABILITYLine-edge and linewidth roughness
LER versus LWR, edge cross-correlation, correlation length, extraction bandwidth, local-CD aperture, and a bounded device-to-SRAM variability bridge
Separate edge from width ->02UV128 SRAM VARIATIONSRAM variation and corner coverage
Condition, lot, wafer, site, replicate, missingness, common-set coverage, variance-component closure, sigma uncertainty, and fixed-condition boundaries
Separate spread from coverage ->02VV129 SPICE EVIDENCESolver convergence and report literacy
Keep solver, numerical, model, metric, and signoff states independent while comparing timestep, tolerances, initial conditions, saved signals, and measurement definitions
Audit a converged result ->03LEARNING TRACKCircuits
CMOS logic, gain, delay, noise margin, and dynamic feedback
Follow circuit path ->04NEW ANALOG PATHAnalog primitives
Current mirror compliance, sense regeneration, headroom, offset, and decision margin
Bias the primitive ->05LEARNING TRACKDigital systems
Controllers, protocols, BIST, ECC, and architecture trade-offs
Trace verified RTL ->06NEW TIMING PATHDigital timing
FO4 delay, VDD, temperature, energy, leakage, and STA slack vocabulary
Time the primitive ->07EXPANDED PATHMemory
SRAM, DRAM/HBM, retention, refresh/ECC guardbands, RowHammer, NAND, 3D NAND, PCM, ReRAM, FeFET, CIM, cache, and test
Follow memory path ->08NEW MEMORY PATHDRAM/HBM & emerging memory
DRAM 1T1C, retention, RowHammer, HBM roofline, NAND, FeFET, MRAM, hierarchy, and CIM
Expand memory ->08BV81 MEMORY SYSTEMHBM/base-die partitioning
DRAM stack, base die, TSV, interposer, PHY, controller, thermal, bandwidth, capacity, and yield tradeoffs
Partition the stack ->09NEW PATHProcess & layout
Surface prep, thermal budget, PVD, etch UQ, feedforward control, APC/FDC decision gates, DRC/LVS, floorplan, PDN/IR, CTS, layout RC, extraction, and timing
Follow physical path ->10NEW SURFACE PATHSurface treatment
O2 plasma, O3 ozone, contact angle, residue, recovery, and adhesion prep
Prepare the interface ->11NEW ANNEAL PATHThermal processing
Annealing, RTA, activation, diffusion, TED, and silicide contacts
Follow the heat budget ->12NEW CLEAN PATHWet clean & adhesion
Contamination removal, native oxide, HMDS, queue time, and evidence needs
Clean the surface ->13NEW PTR PATHPackaging, test & reliability
Package parasitics, thermal stack, wafer sort, guardband, stress, and FA vocabulary
Finish the chip story ->14NEW EQP PATHEquipment & facilities
Cleanroom particles, vacuum, tool availability, utilities, and EHS boundaries
Bound the fab support ->15V78 PROCESS CONTROLPlasma etch and feedforward control
Wafer-aware etch uncertainty, lithography-to-etch control, changing variance, and optimizer caution
Study etch UQ ->16V79 EDA RCPhysical verification and layout RC
DRC/LVS/PEX/timing checkpoints, standard-cell reports, CTS/routing/IR handoff, model-to-measurement evidence, floorplan congestion, IR-drop, clock spine, layout RC, slew, slack, confidence, and signoff boundaries
Trace RC delay ->16BV84 EDA FLOORPLANFloorplan report literacy
Utilization, macro channels, PDN/IR, CTS, routing overflow, timing-risk, and next evidence checks
Read reports ->16CV92 EDA HANDOFFCTS, routing, and IR report handoff
Clock latency/skew, route overflow/completion, extracted RC, static/transient droop, current density, evidence stage, owner view, and replacement slots
Align the reports ->16DV93 OPEN SILICONOpen-silicon model-to-measurement evidence
Model assumptions, cell characterization, implementation reports, test structures, measurement availability, discrepancy, uncertainty, and claim maturity
Trace the evidence ->16EV94 GAUGE R&RGauge R&R and measurement-system analysis
Crossed/nested study design, representative part range, repeatability, operator/tool/interaction reproducibility, bias, linearity, stability, resolution, uncertainty, discrimination, and next evidence checks
Review the measurement system ->17V65 DAILY SIGNALMRAM fundamentals
Switch probability, write energy, read margin, retention, and disturb risk
Open MRAM triangle ->18V65 DAILY SIGNALHybrid bonding
Roughness, stiffness spread, particle state, metrology sigma, and readiness bands
Check readiness ->19V80 VMET PATHMetrology & yield
Small-data virtual metrology, APC/FDC decision gates, uncertainty, adaptive sampling, Cpk proxy, escape risk, and evidence gates
Trust the measurement ->19BV89 PROCESS CONTROLAPC/FDC decision literacy
Equipment-data context, FDC state, VM uncertainty, dynamic sampling, feedforward handoff, false-alarm risk, and owner review
Gate APC evidence ->DEVICE PATH 01 / 25-35 MIN
From a junction field
to restored logic.
Start with charge and potential inside silicon. Then use a gate to control surface charge, and finally connect complementary devices into the smallest restoring logic gate.
8 connected labs316 saved bias points2 simulation engines
01CAUSE -> EFFECT
JUNCTION ELECTROSTATICS
A depletion region stores the built-in field.
Join p-type and n-type silicon and mobile carriers diffuse away from the interface. The uncovered dopants create the field that opposes further diffusion.
Wdep = 0.580 um1D DEVSIM / equilibrium / 300 KInspect equilibrium ->
02CAUSE -> EFFECT
EXTERNAL BIAS
Voltage reshapes the barrier.
Forward bias lowers the junction barrier while reverse bias widens depletion. The solved potential and carrier profiles expose the mechanism behind rectification.
W = 0.381-0.705 um-1.0 V to +0.6 V reproduced sweepBias the junction ->
03CAUSE -> EFFECT
MOS CAPACITOR
Gate bias redistributes charge before it drives current.
A metal gate and thin oxide reshape the silicon surface from hole accumulation through depletion to electron inversion. The gate-charge derivative turns that electrostatics into a C-V curve.
0.6906 -> 0.0325 uF/cm25 nm SiO2 / 61 DEVSIM pointsRead the charge ->
04CAUSE -> EFFECT
MOS ELECTROSTATICS
A gate forms a conducting channel.
Positive gate bias attracts electrons toward the oxide interface. Follow the surface concentration as the channel connects source and drain.
Ion/Ioff = 422x2D drift-diffusion / VDS = 1.0 VForm the channel ->
05CAUSE -> EFFECT
COMPLEMENTARY DEVICES
Two transistors restore logic.
The NMOS pull-down and PMOS pull-up exchange control around the switching point. Device current becomes a rail-to-rail voltage transfer characteristic.
VM = 0.87 VSKY130 TT / 1.8 V / 181 pointsConnect device to circuit ->
06CAUSE -> EFFECT
CFET CONTACT RC
Vertical stacking changes the contact and parasitic evidence.
CFET density is attractive only when contact resistance, local interconnect capacitance, via alignment, thermal coupling, and integration risk are kept beside the circuit-context delay proxy.
1728 CFET rowscontact / via / local RC / no TCADMap CFET ->
07CAUSE -> EFFECT
GAN-SIC HEMT
Substrate, buffer, device, package, and reliability move together.
Semi-insulating SiC can help RF and thermal paths, but the useful claim still needs buffer-trap, dynamic Ron, gate-stack, package thermal, and mission-profile evidence.
2304 GaN/SiC rowssubstrate / buffer / thermal / no recipeTrace GaN/SiC ->
08CAUSE -> EFFECT
DYNAMIC RON
Trap memory turns Ron into a time-window question.
The v88 replay keeps stress class, drain-bias class, recovery window, temperature, switching context, current collapse, measurement caution, and evidence maturity beside the dynamic-Ron ratio.
5120 dynamic Ron rowsstress / recovery / no qualificationRead dynamic Ron ->
09CAUSE -> EFFECT
TCAD DOE
A surrogate optimizer is not evidence by itself.
The v90 replay keeps device context, design lever, DOE plan, surrogate family, objective priority, validation posture, mesh stability, calibration anchor, extrapolation risk, and constraint review beside the pareto-readiness score.
6144 TCAD DOE rowsDOE / surrogate / no live TCADGuard optimizer evidence ->
10CAUSE -> EFFECT
ARCHITECTURE COMPARISON
A newer structure is not a universal winner.
The v91 replay keeps planar MOSFET, FinFET, GAAFET, and CFET context beside electrostatic control, footprint, contact and capacitance burden, variability, thermal coupling, integration risk, evidence maturity, and circuit handoff.
4096 comparison rowscontext / evidence / no architecture rankingCompare architectures ->
11CAUSE -> EFFECT
PHOTONICS CAUSAL CHAIN
Exact photon relations still need device evidence.
The v99 replay links photon energy, LED and laser boundaries, ideal detector responsivity, ring transfer, and MZI phase while keeping material absorption, gain, dispersion, mode convergence, coupling calibration, carrier response, and optical measurement visibly unfilled.
4536 photonics rows5 nodes / 9 sources / 0 mode-FDTD runsTrace photonics evidence ->
12CAUSE -> EFFECT
RF REFERENCE-PLANE CHAIN
A corrected S-parameter still needs an evidence contract.
The v100 replay compares raw, lossless port-extension, symmetric split-fixture proxy, and exact declared-fixture inversion across complex two-port data while keeping calibration, residual error, passivity, stability, noise, causality, uncertainty, and RF signoff separate.
6048 RF rows5 nodes / 12 sources / 0 instrument actionsTrace RF evidence ->
13CAUSE -> EFFECT
2D CFET CONTACT-TO-PPA
A channel result is not yet a circuit claim.
The v101 replay carries declared n/p transport and contact hypotheses through local RC, extraction maturity, compact-model scope, inverter/ring/logic loading, contradiction gates, and owned replacement evidence without ranking a material, architecture, node, or foundry.
6144 CFET rows4 evidence nodes / 9 sources / 0 solver runsTrace contact to PPA ->
14CAUSE -> EFFECT
SNSPD EVENT EVIDENCE
A count is not yet a photon or a mechanism.
The v102 replay carries declared geometry and normalized current distribution through edge or constriction evidence, illuminated and dark contexts, competing mechanism labels, timing and radiometry lineage, uncertainty, contradiction gates, and owned replacement evidence without recommending a detector or operating point.
5184 SNSPD rows6 evidence nodes / 11 sources / 0 solver runsTrace detector evidence ->
15CAUSE -> EFFECT
M3D SRAM INTEGRATION EVIDENCE
A stacked cell is not yet an integration claim.
The v103 replay carries declared device tiers and oxide-semiconductor access transport through contacts, inter-tier links, WL/BL loading, thermal budget, extraction maturity, cell/subarray sensitivities, contradiction gates, and owned replacement evidence without copying a topology or naming an architecture winner.
6144 M3D SRAM rows9 evidence nodes / 11 sources / 0 TCAD or PEX runsTrace integration evidence ->
16CAUSE -> EFFECT
2D HETEROJUNCTION NDR EVIDENCE
A falling point is not yet an NDR mechanism.
The v104 replay separates signed-bias rectification, consecutive negative slope, peak/valley prominence, overlap-window broadening, series/contact burden, matched forward/reverse history, trap-memory contradiction, mechanism ambiguity, and owned replacement evidence.
6144 NDR rows192 sweep pairs / 9 nodes / 5 sources / 0 transport runsTest NDR evidence ->
17DEVICE -> CIRCUIT
THERMOELECTRIC SENSOR CALIBRATION EVIDENCE
A signal is not yet a calibrated temperature.
The v105 replay separates normalized thermoelectric response, series-junction scaling, reference-junction correction, drift, mechanical hysteresis, cross-sensitivity, calibration residual, uncertainty, traceability lineage, contradiction review, and owned replacement evidence.
6144 sensor rows384 configurations / 7 nodes / 7 sources / 0 physical temperaturesTrace calibration evidence ->
THE CONNECTING IDEA
Charge shapes potential.
Potential controls current.
charge->potential->n, p->ID->VOUT
Each arrow is represented by a solved or reproduced artifact. The path changes model fidelity deliberately: drift-diffusion for device electrostatics, then a foundry compact model for circuit behavior.
MEMORY PATH 01 / 25-35 MIN
From stored charge
to a checked response.
Follow memory from SRAM read/write behavior and column mux/I/O into DRAM/HBM locality, 1T1C sensing, retention, refresh/ECC guardbands, RowHammer, NAND, 3D NAND, PCM drift, ReRAM variability, FeFET, MRAM switching/read/retention, hierarchy placement, CIM crossbar tradeoffs, and the synchronous controller contract that exposes memory to a digital system.
8 connected labs16 memory evidence sets1 conceptual sequence map
01NEXT ABSTRACTION
READ OPERATION
Precharge, develop, then sense.
A read begins with both bitlines high. The wordline connects the cell, the stored-zero side develops a small differential, and sensing must wait until that difference is usable.
56.6-247.7 psSKY130A TT / 30-300 fF bitline loadsTrace the read ->
02NEXT ABSTRACTION
BITLINE DIFFERENTIAL
Cell current must create a readable voltage difference.
A lumped 100 fF bitline converts read current into differential voltage. Sense-enable is safe only after the selected threshold is reached.
500 -> 125 ps20 -> 80 uA / 100 mVPlace sense-enable ->
03CELL -> SYSTEM
COLUMN MUX AND I/O
Column selection decides what the sense path actually sees.
The selected local bitline pair passes through a finite column mux into shared sense and output circuitry. Mux ratio, shared load, and write-path off-state loading change the delivered differential and timing.
864 replay rowsmux ratio / load / write off-stateFilter column I/O ->
04CELL -> SYSTEM
STATIC STABILITY
Read access consumes noise margin.
The same access device that exposes the stored state also loads the internal zero node. Overlay the two inverter curves and fit the limiting square to quantify the remaining static margin.
449 -> 279 mV37.9% reduction / ngspice 46 / 1,001 pointsMeasure the butterfly ->
05SRAM -> MEMORY
MEMORY DEPTH
Sense, column I/O, disturb, assist, and cache live in different evidence layers.
A deeper SRAM note must not flatten everything into a single margin. Sense-amplifier decision margin, column mux/I/O, read-disturb sizing, assist taxonomy, and AMAT cache behavior each carry different assumptions and non-claims.
5 promoted simssense / column I/O / disturb / assist / cacheOpen memory depth ->
06CELL -> SYSTEM
MEMORY BEYOND SRAM
DRAM/HBM, retention, NAND, PCM, ReRAM, FeFET, MRAM, hierarchy, and CIM need separate cards.
Memory School now adds DRAM/HBM row-buffer behavior, HBM/base-die partitioning, 1T1C charge sharing, retention, refresh/ECC guardbands, RowHammer, NAND threshold margin, 3D NAND Vt/ECC, PCM drift, ReRAM variability, FeFET hysteresis, HBM roofline, HBM/base-die partitioning, hierarchy placement, MRAM switching/read/retention, and CIM vocabulary.
18 memory/eNVM simsDRAM/HBM / 3D NAND / PCM / ReRAM / MRAM / CIMExpand the hierarchy ->
06BCELL -> SYSTEM
HBM BASE DIE
A base die is where memory-system responsibility can move.
The v81 HBM map compares host controller, controller-in-base, controller/PHY/RAS-in-base, and custom die-to-die wrapper choices against TSV, interposer, thermal, bandwidth, capacity, integration, and yield-risk proxies.
1296 HBM rowsDRAM stack / base die / TSV / interposerPartition HBM ->
06CCELL -> SYSTEM
DRAM GUARD BANDS
Retention, refresh, RowHammer, and ECC must be read together.
The v85 replay keeps temperature, weak-tail cells, access activation pressure, refresh policy, ECC/scrub coverage, residual risk, thermal stress, and next evidence check in one public-safe table.
4096 DRAM rowsrefresh / RowHammer / ECC / no attack workflowTrace DRAM guardband ->
06DCELL -> SYSTEM
EMERGING MEMORY MAP
A memory technology only wins inside a placement context.
The v86 replay compares SRAM, DRAM, HBM, NAND, MRAM, FeFET, ReRAM, PCM, SCM, embedded NVM, eDRAM, and CIM using latency, density, endurance, retention, energy, margin, integration, thermal, and evidence-maturity proxies.
1728 placement rowsMRAM / FeFET / ReRAM / PCM / SCM / HBMMap placement fit ->
07CELL -> SYSTEM
MRAM TRIANGLE
A nonvolatile cell still needs read and disturb evidence.
The MRAM triangle keeps switch probability, write energy, read margin, retention proxy, and disturb risk in one table so one metric cannot dominate the lesson.
18 MRAM rowsSTT / SOT / read / retentionOpen MRAM fundamentals ->
08CELL -> SYSTEM
DYNAMIC WRITE BOUNDARY
Write assist changes the success frontier.
A write drives the internal node through access devices while the cell fights to retain its previous state. Lowering cell VDD during the pulse can move the minimum successful wordline.
1.2 -> 1.0 V24 SKY130 transients / 18 pass / 6 failMap the shmoo ->
09CELL -> SYSTEM
DIGITAL CONTROL
A protocol turns the cell into a usable memory.
Requests are accepted only at a defined edge. The controller sequences address, write data, and a one-cycle response while a self-checking testbench verifies every accepted transaction.
7 / 7 responses18-cycle Icarus trace / 0 assertion failuresFollow the controller ->
THE DESIGN TENSION
Observe the state.
Do not destroy it.
HOLD SNM449mV
-37.9%READ SNM279mV
The SKY130 read sweep makes load-dependent sensing delay visible, the write shmoo exposes a dynamic write-success boundary, and the generic SNM model isolates static stability. These are educational pre-layout results; the controller evidence proves protocol behavior, not analog timing.
DRAM PATH 01 / 15-20 MIN
From stored charge
to a refresh deadline.
Leave the static SRAM latch and follow a dynamic bit instead. The path connects capacitor charge, leakage, a sensing threshold, and the system-level need for periodic refresh.
3 executed SPICE cases30 fF storage node<0.00004% analytical error
01CHARGE -> TIME
STORED CHARGE
A DRAM bit is a voltage on a tiny capacitor.
The baseline begins at 1.2 V on a 30 fF storage node. With the access path closed, leakage is the only modeled discharge path.
30 fF / 1.2 Vlumped storage-node modelInspect the node ->
02CHARGE -> TIME
RETENTION BOUNDARY
Sense margin turns decay into a deadline.
Retention time is measured when the node crosses 0.6 V. Three leakage resistances isolate how a shorter RC time constant reduces that deadline.
20.79 -> 5.20 us1 Gohm -> 250 MohmCompare leakage ->
03TIME -> POLICY
REFRESH POLICY
Refresh must arrive before the sensing limit.
A safe controller schedules refresh with margin below the measured boundary. Moving the marker past 100% makes the stored state explicitly unsafe.
<70% baselineeducational timing marginPlace the refresh ->
THE DYNAMIC MEMORY RULE
Charge is temporary.
Refresh is architectural.
Q->V(t)->VSENSE->tret->REF
The executed baseline isolates RC decay. It does not model a production DRAM cell, access transistor, distributed bitline, sense amplifier, process variation, or a calibrated temperature law.
PROCESS & LAYOUT PATH 01 / 25-35 MIN
From drawn shapes
to measured delay.
Follow process evidence from PVD and etch uncertainty into virtual metrology, surface prep, thermal budget, contact resistance chains, cleaning, and public-safe physical-verification literacy. Every stage keeps the artifact and boundary visible.
18 connected gates9 process evidence sets0 recipe workflows
00DARTIFACT -> GATE
ETCH DEPTH / SELECTIVITY / SURFACE HANDOFF
Etch depth is not one mechanism or one process knob.
The v111 atlas keeps HAR, ALE, selective etch, DRIE, strip and ash, and wet etch distinct while aligning profile, selectivity, transport, mask, residue, surface, metrology, role, and replacement-evidence questions.
41472 rows / 6 familiesone selected CSV at a time / 120 link-only sources / 0 physical recipe valuesChoose the etch family ->
00CARTIFACT -> GATE
REACTIVE-ION ETCH MECHANISM
An etch result is not yet a mechanism claim.
The v109 replay separates ion access, neutral reactivity, passivation, chemical and physical removal, synergy, mask burden, transport, damage, profile control, six regimes, role gates, and the restricted feature-profile bridge.
6912 RIE mechanism rows3456 physical configurations / 18 sources / 0 physical recipe valuesTrace mechanism to profile ->
00BARTIFACT -> GATE
VACUUM / GAS DELIVERY / INVENTORY
A chamber pressure label is not yet a delivery state.
The v108 replay separates gas admission, wall release, chamber and foreline inventory, conductance, nominal and effective pumping, settling, distribution, role gates, and the restricted CCP/ICP bridge.
10368 vacuum-delivery rows5184 physical configurations / 14 sources / 0 physical equipment valuesTrace source to removal ->
00AARTIFACT -> GATE
CCP / ICP CHAMBER STATE
A plasma label is not yet a wafer-facing boundary condition.
The v107 replay separates bounded CCP/ICP architecture, normalized drive, pressure, bias, gas response, wall loss, matching, bulk support, sheath, charged and neutral delivery, energy-angle breadth, radial state, role gates, and the restricted feature-scale bridge.
6144 chamber-state rows3072 physical configurations / 14 sources / 0 physical process valuesTrace source to wafer ->
00ARTIFACT -> GATE
PARTICLE MONTE CARLO TOPOGRAPHY
A flux response is not yet a feature profile.
The v106 replay connects normalized source direction, species mix, surface interaction, reflection, secondary transport, exact conservation, and 16 saved geometry states for directional RIE and sputter trench deposition.
6144 topography rows192 physical configurations / 8 sources / 0 physical process valuesFollow the evolving profile ->
01ARTIFACT -> GATE
PVD COVERAGE
Blanket thickness is not step coverage.
PVD and sputter films can look healthy on open areas while high-aspect-ratio features lose bottom and sidewall continuity. The useful evidence separates blanket thickness, bottom coverage, sidewall coverage, and overhang risk.
15 casesPVD step-coverage replayInspect coverage ->
02ARTIFACT -> GATE
ETCH UQ
An etch window has profile, selectivity, CD, and location variation.
Plasma etch learning should not expose a recipe. It should show anisotropy, selectivity, CD bias, wafer location, and pass-probability proxy as separate evidence claims.
27 casesplasma etch UQ replayOpen etch UQ ->
03ARTIFACT -> GATE
FEEDFORWARD CONTROL
A lithography measurement can move an etch decision.
The v78 replay links post-lithography CD/overlay, resist/focus state, feedforward action, post-etch CD, Cpk proxy, and inverter-delay proxy without exposing recipes.
1296 feedforward rowslithography / etch / Cpk / delayReplay feedforward ->
03BARTIFACT -> GATE
VIRTUAL METROLOGY
Sparse measurements need uncertainty before trust.
Virtual metrology can reduce physical sampling only when data age, sensor health, sample fraction, model family, uncertainty, guardband, escape risk, and the next physical measurement remain visible.
2880 VM rowssmall-data VM / adaptive sampling / no release ruleGate the prediction ->
ARTIFACT -> GATE
APC/FDC
Process-control language needs a decision gate.
The v89 replay keeps signal quality, FDC state, VM uncertainty, sampling coverage, feedforward handoff, false-alarm risk, wafer-at-risk proxy, and role review beside the decision-readiness score.
6144 APC/FDC rowssignals / sampling / no control actionGate the evidence ->
04ARTIFACT -> GATE
SURFACE PREPARATION
The next film starts at the surface.
O2 plasma and O3 / UV-ozone can remove organics and raise wettability before deposition, bonding, or adhesion work. The useful claim keeps contact angle, recovery, oxide caution, and material compatibility visible.
8.43 deg / 96.3%O2 plasma and UV-O3 surface replaysPrepare the interface ->
05ARTIFACT -> GATE
THERMAL PROCESSING
Heat activates, repairs, and redistributes.
Annealing can electrically activate dopants and repair implant damage, but it can also broaden junctions, feed TED tails, and change contact reactions. The useful claim keeps thermal budget, activation, diffusion, and metrology visible.
91.71% / 16.52 nmRTA, thermal budget, TED, and silicide replaysFollow the anneal ->
06ARTIFACT -> GATE
CONTACT RC CHAIN
A contact module can move a circuit delay.
The v72 browser chain links surface/contact preparation, silicide anneal, contact area, activation proxy, Rc/Rsd proxy, ring oscillator delay proxy, and SRAM bitline delay proxy in one replaceable table.
144 chain rowscontact Rc / RO / bitline proxiesTrace the chain ->
07ARTIFACT -> GATE
WET CLEAN
Cleaning changes the surface state, not just the particle count.
Wet clean, native oxide control, and HMDS adhesion prep should name organics, particles, metals, oxide state, hydrophobicity, queue time, and downstream intent separately.
16 evidence needswet clean, native oxide, HMDS, and sequence replaysMap the surface state ->
08ARTIFACT -> GATE
DESIGN RULE CHECK
Geometry must satisfy the process.
Load the official SKY130 inverter GDS with the pinned technology rules. DRC checks widths, spaces, enclosures, and other manufacturability constraints before connectivity is trusted.
0 DRC errorsMagic 8.3.681 / pinned SKY130AInspect the GDS ->
09ARTIFACT -> GATE
LAYOUT VS SCHEMATIC
Shapes must implement the intended circuit.
Extraction converts polygons into devices and nets. Netgen then compares that result with the official source circuit, including pins, device counts, and topology.
LVS match uniqueNetgen 1.5.323 / official INV sourceProve connectivity ->
10ARTIFACT -> GATE
PARASITIC EXTRACTION
Physical proximity adds a hidden network.
The extracted circuit retains the two intended MOS devices and adds coupling capacitances created by the layout. Those parasitics are the bridge from geometry to electrical consequence.
14 C / 1.424 fF2 MOS devices / Magic extractionOpen the PEX evidence ->
11ARTIFACT -> GATE
LAYOUT RC DELAY
A route can move slew and slack before signoff.
Wire length, layer class, route style, fanout load, and checkpoint stage change RC, delay, slew, and slack-risk proxies. The public replay teaches the evidence order without publishing SPEF, Liberty, SDC, PDK, or tool reports.
3072 RC rowslayout RC / slew / slack ladderTrace RC delay ->
08BARTIFACT -> GATE
FLOORPLAN REPORTS
Floorplan pressure appears before signoff reports.
The v84 replay links utilization, macro channels, PDN obstruction, routing congestion, IR-drop, clock sink spread, skew, insertion delay, and timing-risk proxies to the next safe evidence check.
4096 floorplan rowscongestion / IR / CTS / no live flowRead floorplan reports ->
08CARTIFACT -> GATE
STDCELL REPORTS
Drive strength only matters with load, slew, area, and evidence stage.
The v87 replay links standard-cell archetype, drive strength, input slew, output load, report stage, optimization goal, pin capacitance, setup/hold slack, max-cap/slew risk, and area/power pressure.
3456 standard-cell rowsLiberty / STA / no copied cellsRead stdcell reports ->
08DARTIFACT -> GATE
EDA REPORT HANDOFF
Three green snapshots can still describe different checkpoints.
The v92 replay juxtaposes verified clock-tree, routing, and power-grid fixture states, then gates reuse on report stage, extracted RC, activity/current context, cross-report consistency, replacement evidence, and owner review.
4096 handoff rowsCTS / route / IR / no signoffAlign report evidence ->
08FARTIFACT -> GATE
GAUGE R&R / MSA
Separate variance components from reference and stability evidence.
The v94 replay distinguishes study-design defects, representative part spread, repeatability, operator/tool/interaction reproducibility, bias, range linearity, stability/drift, resolution, uncertainty review, discrimination, and accountable next checks without publishing a production pass/fail band.
4096 measurement-system rows15 gates / 0 real measurements / 0 acceptance thresholdsReview Gauge R&R evidence ->
08EARTIFACT -> GATE
MODEL TO MEASUREMENT
A green flow is evidence about checks, not proof of silicon behavior.
The v93 replay separates model assumptions, cell characterization, implementation checkpoints, test-structure intent, author-claim metadata, synthetic teaching pairs, empty owned measurement slots, discrepancy, uncertainty, and bounded claim maturity.
4096 evidence rows0 real measurements / no copied repository dataTrace claim maturity ->
12ARTIFACT -> GATE
POST-LAYOUT TIMING
Parasitics become measurable delay.
Run schematic and extracted netlists under the same TT, 1.8 V, 27 C, 5 fF condition. The post-layout waveform shifts because physical capacitance must also be charged and discharged.
+8.5% / +10.4%tPHL / tPLH change / ngspice 42Compare the waveforms ->
12ARTIFACT -> GATE
DISTRIBUTED INTERCONNECT
Where capacitance sits changes the observed delay.
Hold total wire R and C constant, then divide the path into one, three, and five sections. The 50% delay converges as the ladder better represents a distributed wire.
83.21 -> 59.77 ps1 -> 5 sections / Elmore cross-checkDistribute the wire ->
13ARTIFACT -> GATE
COUPLING NOISE
A switching neighbor can disturb a quiet net.
Increase coupling capacitance while the aggressor transition and victim load stay fixed. Peak victim noise and recovery time both rise with coupling.
39.6 -> 194.2 mV5 -> 30 fF coupling / ngspice 42Measure the victim ->
14PHYSICAL -> ELECTRICAL
POWER INTEGRITY
Current turns rail resistance into local supply loss.
Increase load current while the five-section rail stays fixed. The voltage gradient steepens, and the endpoint drop follows the same I x R identity at every executed operating point.
2.5 -> 10.0 mV10 -> 40 mA / 250 mOhm / ngspice 42Trace the rail ->
THE EVIDENCE CHAIN
Geometry becomes
an electrical model.
GDS->DRC->LVS->PEX->delta t
The reproduced baseline uses the official sky130_fd_sc_hd__inv_1 cell, the v79 replay adds a public-safe RC-to-delay ladder, v84 adds floorplan/congestion/IR/CTS report literacy, and v92 adds same-checkpoint CTS/routing/IR handoff, and v93 adds a zero-real-measurement model-to-silicon evidence ladder, and v94 adds Gauge R&R measurement-system decision literacy. These validate evidence order and report literacy; they do not claim that a custom SRAM layout, macro, or product has passed signoff.
EQUIPMENT FACILITIES PATH 01 / 20-30 MIN
From fab support
to bounded evidence.
Process results depend on the environment around the wafer. This path names cleanroom, vacuum, equipment-state, and utilities evidence without creating facility operation or equipment-control workflows.
4 equipment/facility cards112 simulation objects0 facility workflows
01SUPPORT EVIDENCE
CLEANROOM PARTICLES
Cleanroom evidence starts as a classification question.
A useful claim separates traffic, air-change proxy, particle burden, mini-environment effect, recovery, and excursion vocabulary before saying anything about wafer impact.
0.14 burden proxyISO 14644 vocabulary anchor / no certificationRead the particle budget ->
02SUPPORT EVIDENCE
VACUUM ENVELOPE
Pumpdown time depends on condition, not magic.
Volume, effective speed, target pressure, and leak floor belong next to any vacuum claim. The public card teaches the envelope without valve, leak-check, or interlock instructions.
56.6 snominal chamber teaching caseTrace pumpdown ->
03SUPPORT EVIDENCE
EQUIPMENT STATE
Availability is not the same as utilization.
SEMI E10-style language keeps productive, standby, engineering, scheduled downtime, unscheduled downtime, and queue pressure in separate evidence fields.
86.31%availability in RAM-improvement teaching weekRead tool state ->
04OPERATION BOUNDARY
FACILITY UTILITIES
Utility claims need lanes.
Cleanroom air, vacuum/exhaust, UPW/cooling, precision support, and abatement should stay visible before a sustainability, capacity, or process-support claim is reused.
135 MWhhigh-vacuum lithography shift teaching caseOpen utilities lanes ->
PACKAGING TEST RELIABILITY PATH 01 / 20-30 MIN
From assembled silicon
to bounded evidence.
Move beyond front-end fabrication into the job families that turn die into screened products: package electricals, heat flow, wafer sort, reliability stress, and failure-analysis vocabulary.
5 PTR simulation cards39 public experiments0 qualification workflows
01PRODUCT EVIDENCE
PACKAGE PARASITICS
The package adds an electrical network.
Wirebonds, bumps, interposers, and 3D/chiplet connections change loop inductance, coupling capacitance, delay, and PDN impedance. Treat them as evidence fields, not packaging adjectives.
80 pH / 5 psfour teaching package casesBudget package RLC ->
02PRODUCT EVIDENCE
THERMAL PATH
Heat must cross every layer.
A thermal claim needs junction-to-case, case-to-ambient, power, boundary condition, and hotspot context before it becomes useful in a paper or design note.
15 C/WthetaJA stack replayAdd the stack ->
03PRODUCT EVIDENCE
TEST GUARD BAND
Yield and quality risk move together.
Tighter guardbands can lower estimated escapes while also lowering effective yield and increasing retest load. The page keeps those lanes separate.
83% / 900 ppmbalanced teaching caseRead the bins ->
04PRODUCT EVIDENCE
RELIABILITY STRESS
Stress evidence has a statistics boundary.
The bathtub curve helps organize infant mortality, useful life, wearout, and stress-mode vocabulary. It does not prove qualification without sample size, failures, and confidence rules.
4 stress modesbathtub vocabulary replayTrace stress modes ->
05RELEASE BOUNDARY
HYBRID BONDING
Bonding readiness needs mechanical evidence.
Roughness, stiffness spread, particles, and metrology sigma belong together before a hybrid-bonding claim is reused.
27 readiness rowsroughness / stiffness / particlesCheck readiness ->
CIRCUIT PATH 01 / 20-30 MIN
From a transfer curve
to a clock.
A static inverter curve tells us where logic switches. A transient ring tells us how quickly it can happen. Follow the same SKY130 technology across both views.
2 connected labs10 reproduced cases1 pinned PDK
01NEXT
STATIC TRANSFER
An inverter restores logic.
Sweep VIN from 0 to VDD. The PMOS and NMOS exchange control through a narrow high-gain region, turning an analog transfer curve into robust digital levels.
VM = 0.87 V181-point SKY130 TT sweepExplore the VTC ->
02NEXT
NOISE IMMUNITY
Gain creates usable margin.
VIL and VIH are found where the sampled slope crosses -1. Their distance from the output rails estimates how much unwanted voltage a logic level can tolerate.
NML 0.73 V / NMH 0.81 Vmaximum sampled |gain| = 11.90Inspect margin markers ->
03NEXT
DYNAMIC DELAY
Capacitance makes switching take time.
A gate must source or sink charge before its output crosses the next gate's threshold. More load stretches propagation delay even when the DC truth table is unchanged.
td = 62.4 ps3 stages / 5 fF per stageChange the load ->
04LAB
FEEDBACK
An odd loop turns delay into frequency.
Three inversions cannot settle consistently. A transition keeps circulating, and the measured period exposes the accumulated rise and fall delay of the chain.
f = 2.671 GHzSKY130 HD inverter / 1.8 V / TT / 27 CRun the ring ->
THE CONNECTING IDENTITY
One loop makes delay measurable.
f=1/2 N td
For an N-stage odd ring, one period contains two transitions through every stage. This is an extraction identity for the reproduced waveform, not a claim that every edge or stage is perfectly identical.
DIGITAL SYSTEMS PATH 01 / 20-30 MIN
From a protocol edge
to a protected response.
Move from functional memory access to structural self-test and error correction. Explicit contracts and executed traces distinguish detection from safe recovery.
3 executed RTL labs92 ECC injection cases332 saved digital events
01CONTRACT -> TEST
PROTOCOL CONTRACT
A request becomes one checked response.
Start from the controller acceptance edge, address and data capture, and the one-cycle response contract proved by the existing self-checking trace.
7 / 7 responses18 cycles / 0 assertion failuresTrace the protocol ->
02CONTRACT -> TEST
MARCH ALGORITHM
A deterministic walk exposes memory faults.
March C- writes and reads every address in ascending and descending order. Ten operations per cell preserve linear complexity while sensitizing stuck-at faults.
10N / 80 accesses8 words x 8 bits / six elementsWalk March C- ->
03CONTRACT -> TEST
FAULT EVIDENCE
A mismatch becomes a diagnostic event.
Compare the fault-free trace with injected stuck-at-0 and stuck-at-1 scenarios. The lab preserves every cycle and points to the first observable failure.
0 / 2 / 3no fault / SA0 / SA1 mismatchesInspect detection ->
04FAILURE -> EVIDENCE
ERROR CORRECTION
Protection changes what the system may safely return.
SECDED adds five parity bits to eight data bits. Every single codeword-bit error is corrected; every double-bit pair is detected and explicitly withheld as uncorrectable.
13 / 13; 78 / 78single corrected; double detectedExplore SECDED ->
THE VERIFICATION LOOP
Stimulate. Observe.
Compare. Localize.
REQ->TEST->ECC->FIX->FLAG
The browser replays executed Icarus evidence. It does not synthesize arbitrary HDL. BIST covers a single-cell stuck-at model; ECC covers one fixed payload and digital bit flips, not analog cell failures.
MODEL BOUNDARY
Know what the number means.
The paths deliberately cross model boundaries: educational drift-diffusion, foundry compact models, generic SRAM stability, verified RTL, and an official-cell physical baseline. None replaces custom-macro post-layout PVT characterization or measured silicon.
Open the first lesson packet ->EVIDENCE TRAIL
Move from claim to artifact.
Each lab exposes conditions, extraction rules, limitations, datasets, and downloadable netlists. Research keeps executed evidence separate from indexed sources, and worksheets test whether the boundary was understood before reuse.
Open the first worksheet ->