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SASemiAgoraSemiconductor knowledge & engineeringOpen lesson

SIMULATION / SA-PTR-THERMAL-STACK-001

Package thermal resistance stack
Thermal Stack

Add junction-to-case and case-to-ambient resistance while keeping hotspot coupling visible.

sectionExploresectionRun CardsectionExportsectionMethodssectionLimitssectionEvidence

EXPLORE

Start with the observable.

Use this page when the simulation is the primary artifact. The linked lesson explains the concept; the linked lab keeps the visual replay surface available.

guided exploration
  • Add thermal-resistance components before reading any maximum-power statement.
  • Compare hotspot coupling separately from total thetaJA.
  • Use the card to decide what boundary condition belongs next to a thermal claim.
Open visual lab ->Open lesson ->

RUN CARD

Conditions before conclusions.

The public page replays saved thermal-stack teaching data. It does not perform thermal simulation or product thermal design.

precomputed replay

Primary knobs

  • Teaching cases: plastic wirebond, flip-chip with heat spreader, 2.5D interposer/lid, stacked 3D hotspot case
  • Outputs: thetaJC, thetaCA, thetaJA, 60 C power budget, hotspot coupling index
  • Review focus: stack addition and hotspot caution
  • Boundary: no heat-sink recommendation, thermal qualification, or product power limit
outputs

Saved outputs

  • thermal stack table
  • series-resistance check
  • lowest theta case marker
  • hotspot caution marker

EXPORT

Download the public artifacts.

These exports are the supported public files for review. PDK files and restricted third-party material are not redistributed.

download

Dataset JSON

/data/ptr-thermal-resistance-stack-web-v1.json

Open file ->

METHODS

How the number was made.

Methods are written for citation discipline: the extraction rule matters as much as the plotted value.

method

Compute thetaJA as thetaJC plus thetaCA for each teaching case.

Keep this method attached when reusing the figure or metric.

method

Compute a simple max power marker from a 60 C rise divided by thetaJA.

Keep this method attached when reusing the figure or metric.

method

Track hotspot coupling separately because local heating can worsen even when package-level resistance improves.

Keep this method attached when reusing the figure or metric.

method

Keep boundary conditions and non-claims attached to every thermal number.

Keep this method attached when reusing the figure or metric.

LIMITS

What this page does not claim.

The MVP is useful because the limits are visible. These statements prevent a teaching simulation from being cited as silicon evidence.

non-claim

No calibrated package thermal model, transient thermal impedance, TIM stack, airflow model, heat-sink design, or product power limit is included.

Carry this boundary into any derivative note, paper draft, or slide.

non-claim

No reliability derating, board environment, package vendor model, or customer thermal specification is represented.

Carry this boundary into any derivative note, paper draft, or slide.

non-claim

The hotspot index is a teaching proxy and cannot rank real packages.

Carry this boundary into any derivative note, paper draft, or slide.

non-claim

Real reuse requires measured or vendor-qualified thermal data, boundary conditions, uncertainty, and product-owner signoff.

Carry this boundary into any derivative note, paper draft, or slide.

EVIDENCE

Trace the claim back to artifacts.

The evidence route remains the catalog-level browser; this page is the simulation-level reading card.

evidence note

The dataset preserves four package thermal teaching cases.

SA-PTR-THERMAL-STACK-001

evidence note

Verification checks thetaJA totals, lowest total resistance, and increased 3D hotspot risk.

SA-PTR-THERMAL-STACK-001

evidence note

The model card keeps thermal design and reliability-release boundaries explicit.

SA-PTR-THERMAL-STACK-001

Source spine

These links anchor the public teaching model. They do not convert the replay into a qualified process recipe or signoff result.

NIST National Advanced Packaging Manufacturing ProgramPublic NIST page framing advanced packaging challenges around power, heat, test, repair, and reliability.NIST advanced semiconductor packaging material needsPublic NIST publication page on packaging materials, metrology, moisture reliability, residual stress, warpage, and reproducibility.SEMI Heterogeneous Integration RoadmapPublic roadmap page connecting assembly, packaging, interconnect, test, thermal management, and reliability.

Public execution boundary

No server-side live ngspice execution, uploads, accounts, payments, comments, newsletter signup, or job/event submissions are active on this page.