Packaging changes the circuit you thought you had.
Interconnect length, loop inductance, capacitance, and PDN impedance can reshape delay and noise before a signal reaches the board.
80 pH / 5 ps / open simulation ->LESSON PACKET / SA-PTR-001
Packaging, test, and reliability.
Finish the chip story.
Front-end process builds devices, but products still need assembly, power delivery, heat removal, screening, and reliability evidence. This packet makes that back-end chain visible without turning the site into a release system.
BACK-END EVIDENCE CHAIN
Package, test, and reliability are not afterthoughts.
The track gives students a job-family view of the back end while giving researchers quick access to reusable, bounded simulation cards.
Heat flow is a stack problem.
Junction-to-case, case-to-ambient, and hotspot coupling should be read together before a power or reliability claim is reused.
15 C/W low case / open simulation ->A stricter test limit trades yield for escape risk.
Guardband, top-bin fraction, estimated escapes, and retest load are separate evidence lanes, not one magic pass/fail number.
900 ppm balanced / open simulation ->The bathtub curve is a vocabulary map, not a warranty.
Infant mortality, useful life, wearout, and accelerated stress modes belong in the same review packet with clear non-claims.
4 stress modes / open simulation ->SIMULATION BUNDLE
Start from the card if you are writing a paper.
Each object carries Explore, Run Card, Export, Methods, Limits, Evidence, and source links. The lesson explains context; the simulation pages carry the citable boundary.
Package parasitics RLC budget
Compare teaching package cases by loop inductance, coupling capacitance, signal delay, and PDN impedance.
Open Package RLC ->Package thermal resistance stack
Add junction-to-case and case-to-ambient resistance while keeping hotspot coupling visible.
Open Thermal Stack ->Wafer sort binning and guardband
Replay a teaching guardband tradeoff between yield, top bin, estimated escapes, and retest load.
Open Wafer Sort ->Reliability stress and bathtub curve
Connect infant mortality, useful life, wearout, and accelerated stress vocabulary without claiming qualification.
Open Reliability Stress ->SOURCE SPINE
Public sources anchor the vocabulary and non-claims.
NIST and SEMI/IEEE sources frame advanced packaging as a power, heat, test, repair, reliability, materials, and metrology problem. SemiAgora adds only teaching replays here.
NIST National Advanced Packaging Manufacturing Program
https://www.nist.gov/chips/research-development-programs/national-advanced-packaging-manufacturing-program
Open source ->NIST advanced semiconductor packaging material needs
https://www.nist.gov/publications/material-needs-and-measurement-challenges-advanced-semiconductor-packaging
Open source ->NIST reliability metrology for semiconductors
https://www.nist.gov/publications/reliability-metrology-semiconductor-industry-nist
Open source ->SEMI Heterogeneous Integration Roadmap
https://www.semi.org/en/communities/heterogeneous_integration_roadmap
Open source ->DATA TO COLLECT NEXT
PTR becomes valuable when evidence type and release boundary are separated.
The next upgrade is not a production workflow. It is a rights-clean evidence library with uncertainty, sample count, and clear non-claims.
Rights-clean package parasitic examples with package family, frequency range, extraction boundary, and uncertainty
Attach method, units, source rights, sample count, confidence or uncertainty, and the strongest thing the result still does not prove.
Thermal-resistance or transient-thermal summaries with power, boundary condition, stack description, and hotspot note
Attach method, units, source rights, sample count, confidence or uncertainty, and the strongest thing the result still does not prove.
Wafer-sort or final-test example tables that expose limits, retest policy, and bin counts without production programs
Attach method, units, source rights, sample count, confidence or uncertainty, and the strongest thing the result still does not prove.
Reliability stress summaries that separate sample size, stress condition, failure definition, censoring, and confidence
Attach method, units, source rights, sample count, confidence or uncertainty, and the strongest thing the result still does not prove.
Failure-analysis evidence ladders for optical inspection, X-ray, SAM, cross-section, emission microscopy, and electrical localization
Attach method, units, source rights, sample count, confidence or uncertainty, and the strongest thing the result still does not prove.
Glossary cards for wirebond, flip-chip, interposer, fan-out, chiplet, PDN, wafer sort, binning, guardband, HTOL, HAST, and FIT
Attach method, units, source rights, sample count, confidence or uncertainty, and the strongest thing the result still does not prove.
Public boundary
No live tester workflow, account, upload, payment, comment, newsletter signup, job/event submission, product release, package signoff, reliability release, or customer-quality workflow is active in this MVP.