5 ps3D teaching delayUNKNOWNInspect metric contract
180 pHInterposer inductanceUNKNOWNInspect metric contract
97.5%Wirebond to 3D L dropUNKNOWNInspect metric contract
SIMULATION / SA-PTR-PKG-PARASITICS-001
Package parasitics RLC budget
Package RLC
Compare teaching package cases by loop inductance, coupling capacitance, signal delay, and PDN impedance.
EXPLORE
Start with the observable.
Use this page when the simulation is the primary artifact. The linked lesson explains the concept; the linked lab keeps the visual replay surface available.
- Compare wirebond, flip-chip, interposer, and 3D/chiplet teaching cases before reusing a package claim.
- Read inductance, capacitance, signal delay, and PDN impedance as separate evidence lanes.
- Use the card to ask which extraction or measurement would be needed for a real package.
RUN CARD
Conditions before conclusions.
The page replays saved package-parasitics teaching data. It does not run field solvers, package extraction, or signoff workflows.
Primary knobs
- Teaching cases: wirebond QFN, flip-chip BGA, 2.5D interposer, 3D/chiplet stack
- Outputs: loop inductance, coupling capacitance, signal delay, PDN impedance
- Review focus: trend literacy across integration styles
- Boundary: no package design file, SI/PI signoff, board stackup, or production package claim
Saved outputs
- package parasitic table
- inductance and delay ordering checks
- PDN impedance ordering check
- source-spine note
EXPORT
Download the public artifacts.
These exports are the supported public files for review. PDK files and restricted third-party material are not redistributed.
Dataset JSON
/data/ptr-package-parasitics-rlc-web-v1.json
Open file ->Model script
/data/ptr_models.py
Open file ->PTR model card
/data/ptr-model-card.md
Open file ->METHODS
How the number was made.
Methods are written for citation discipline: the extraction rule matters as much as the plotted value.
Represent each package family as a teaching case with normalized, public-safe parasitic proxies.
Keep this method attached when reusing the figure or metric.
Check whether integration trend decreases loop inductance, signal delay, and PDN impedance.
Keep this method attached when reusing the figure or metric.
Keep capacitance visible because shorter interconnect does not mean every parasitic decreases.
Keep this method attached when reusing the figure or metric.
Attach source vocabulary without publishing package design rules or product extraction data.
Keep this method attached when reusing the figure or metric.
LIMITS
What this page does not claim.
The MVP is useful because the limits are visible. These statements prevent a teaching simulation from being cited as silicon evidence.
No product package design, field-solver extraction, board stackup, SI/PI signoff, or production package decision is included.
Carry this boundary into any derivative note, paper draft, or slide.
No calibrated frequency-dependent RLC model, S-parameter, decap plan, or package/board co-design result is modeled.
Carry this boundary into any derivative note, paper draft, or slide.
The cases are teaching proxies and cannot be used for package selection or product release.
Carry this boundary into any derivative note, paper draft, or slide.
Real reuse requires qualified extraction, measurement, package vendor data, thermal context, and product-owner signoff.
Carry this boundary into any derivative note, paper draft, or slide.
EVIDENCE
Trace the claim back to artifacts.
The evidence route remains the catalog-level browser; this page is the simulation-level reading card.
The dataset preserves four public-safe package teaching cases.
SA-PTR-PKG-PARASITICS-001
Verification checks inductance, delay, and PDN impedance ordering.
SA-PTR-PKG-PARASITICS-001
The model card keeps package design, SI/PI, and product release boundaries explicit.
SA-PTR-PKG-PARASITICS-001
Source spine
These links anchor the public teaching model. They do not convert the replay into a qualified process recipe or signoff result.
NIST National Advanced Packaging Manufacturing ProgramPublic NIST page framing advanced packaging challenges around power, heat, test, repair, and reliability.SEMI Heterogeneous Integration RoadmapPublic roadmap page connecting assembly, packaging, interconnect, test, thermal management, and reliability.
Public execution boundary
No server-side live ngspice execution, uploads, accounts, payments, comments, newsletter signup, or job/event submissions are active on this page.