Practice Bank
HDLBits, All About Circuits, ChipVerify, and university sites keep learners returning with repeated questions.
- Surface
- Static evidence prompts with answer reveal and limitation field.
- Route
- /practice#evidence-practice-bank
SEMIAGORA RESOURCES
SemiAgora Resources is a link-only, rights-aware catalog. It points to official sources and records why each resource matters; it does not mirror PDFs, articles, code, PDK files, datasets, commercial courseware, publisher figures, or paid content.
BENCHMARK GAP CLOSURES
Five benchmark gaps are now represented as public site surfaces: practice bank, course packets, fixed-data calculators, a live reproducible GitHub package, and atlas search/filter.
HDLBits, All About Circuits, ChipVerify, and university sites keep learners returning with repeated questions.
MIT OCW and edX make syllabus, notes, assignments, exams, and outcomes obvious.
Portal and practice sites give users a small thing to do immediately.
OpenROAD, Tiny Tapeout, FOSSi, and VSD turn learning into inspectable artifacts.
Large portals work because users can search by topic, role, tool, and route instead of scrolling.
SEMICONDUCTOR TOPIC COVERAGE
Daily scans now convert broad public topic signals into lanes, coverage status, next study actions, and rights boundaries. The goal is breadth with source discipline: links and original SemiAgora summaries, not copied libraries.
Link-first source discovery only; no wholesale mirroring.
CC0-1.0 via GitHub API spot check on 2026-08-19Use the matrix to decide which learning packets, simulation seeds, and literature review queues should be promoted next.
2026-08-31-v116RF S-parameter and de-embedding evidence replay, Semiconductor photonics causal-chain replay, Gauge R&R and metrology-system decision replay, Open-silicon model-to-measurement evidence ladder, CTS, routing, and IR-drop report handoff replay, MOSFET, FinFET, GAAFET, and CFET architecture comparison replay, TCAD DOE and surrogate optimization replay, APC, FDC, and feedforward decision replay, GaN dynamic-Ron and trap-memory replay, Standard-cell delay, area, and pin-cap report replay, Emerging memory placement and reliability map, DRAM refresh, RowHammer, and ECC guardband replay, Floorplan congestion, IR-drop, and clock-spine replay, GaN-on-SiC HEMT substrate chain, CFET contact/interconnect parasitics, HBM/base-die partitioning, Small-data virtual metrology replay, etch UQ replay, SKY130 physical verification checkpoint replay, Lithography-to-etch feedforward control replay, and Layout RC delay evidence ladder are now tracked as public, bounded study surfaces.
No recipe, PDK, signoff, or live solver claim.films, pattern transfer, etch, lithography, CMP
EUV, focus/exposure, defect prediction
hybrid bonding, chiplets, interposer, FA
2.5D/3D, interposer, power integrity
HBM roofline, HBM/base-die partitioning, DRAM reliability guardbands, hierarchy, emerging-memory placement, and thermal limits
MRAM, FeFET/FeRAM, ReRAM, PCM, 3D NAND, 3D DRAM/HBM, eDRAM/MIMCAP, SCM/CXL memory, embedded NVM, CIM, placement, reliability, and integration evidence
OpenROAD/OpenSTA report literacy, physical verification, floorplan, CTS, routing, extracted RC, PDN/IR, standard-cell characterization, and model-to-measurement evidence maturity
device simulation, contextual MOSFET/FinFET/GAAFET/CFET comparison, TCAD DOE, GAA, CFET, GaN-on-SiC HEMT, and quantum device watch
photon-semiconductor interaction, emitters, detectors and solar boundaries, waveguides and resonators, and silicon modulator literacy
FinFET, GAA, CFET, contacts, vias, local interconnect, and parasitics
SPC, inline and virtual metrology, APC/FDC evidence gates, Gauge R&R, and measurement-system analysis
role maps, curricula, skill ladders
small-signal parameters, fT and fmax definitions, RF noise, transmission-line effects, reference impedance, calibration boundaries, and device de-embedding literacy
2D CFET transport and contact hypotheses, local parasitic RC, extraction and compact-model maturity, circuit delay/energy/area handoff, contradiction review, and owned replacement evidence
SNSPD geometry and normalized current distribution, edge/constriction evidence, illuminated and dark contexts, mechanism ambiguity, timing/radiometry lineage, uncertainty, contradictions, and owned replacement evidence
Monolithic-3D tier assignment, oxide-semiconductor access transport, contacts, inter-tier connectivity, WL/BL loading, thermal budget, extraction maturity, cell/subarray sensitivities, contradictions, and owned replacement evidence
Signed bias, gate-controlled alignment, overlap-window broadening, monotonic background, series/contact burden, consecutive-slope NDR, rectification, sweep history, trap-memory contradiction, mechanism ambiguity, and owned replacement evidence
Normalized temperature difference, series-junction scaling, Seebeck-contrast class, reference-junction state, drift, mechanical hysteresis, cross-sensitivity, calibration residual, repeatability, uncertainty, traceability lineage, contradiction review, and owned replacement evidence
Directional RIE and sputter trench deposition, aspect ratio, source direction, species mix, surface interaction, reflection/re-emission, secondary transport, exact geometry, conservation, profile risk, evidence posture, and replacement evidence
CCP and ICP reference archetypes, normalized drive, pressure, bias, gas response, wall loss, matching, radial delivery, plasma density, sheath burden, ion/neutral flux, IEDF/IADF breadth, role gates, feature bridge, and replacement evidence
Flow-model regime, gas admission, wall release, conductance, nominal and effective pumping, chamber and foreline inventory, settling, accumulation, distribution, exact ledgers, role gates, plasma bridge, and replacement evidence
Surface family, ion drive, neutral reactivity, passivation, directionality, mask resilience, feature access, six mechanism regimes, exact ledgers, role gates, upstream vacuum/plasma context, feature-profile handoff, and replacement evidence
Variation family, device evidence, circuit margin, reliability-yield evidence, measurement-model traceability, genealogy, role review, exact ledgers, upstream packet postures, and human-reviewed public-atlas handoff
HAR profile evolution, ALE cycle completeness, selective-etch surface fate and lateral recess, DRIE cycle and feature transport, strip and ash residue handoff, wet-etch reaction and geometry, role gates, exact ledgers, source coverage, and replacement evidence
PVD transport and feature access, CVD reaction and conformality, ALD saturation and cycle separation, furnace thermal and batch history, epitaxy interface and strain, selective-deposition surface contrast, ECD seed and gap-fill, role gates, exact ledgers, source coverage, and replacement evidence
Mask data and reticle control, substrate and wafering quality, scanner-track imaging and resist response, implant beamline and wafer interaction, thermal history, clean-surface state, CMP removal and endpoint, role gates, exact ledgers, source coverage, and replacement evidence
Endpoint signal formation and interpretation, inspection and measurement-system evidence, chamber lifecycle, matching, drift and FDC, maintenance evidence, edge, bevel and backside inspection, role gates, exact ledgers, source coverage, traceability, and replacement evidence
Cluster routing and handoff state, facility utilities and material-flow context, exhaust and abatement evidence, resource metering, operating-state attribution, emissions and allocation boundaries, role gates, exact ledgers, source coverage, traceability, assurance, and replacement evidence
Bonding interfaces, thinning and singulation, probe contact and measurement, retest and coverage, panel placement and warpage, RDL lithography, molding and plating, role gates, exact ledgers, source coverage, traceability, reliability, qualification, and replacement evidence
RESOURCE ATLAS
FIRST PICKS TO BUILD AROUND
A strong model for packaging a semiconductor course with syllabus, readings, lecture notes, assignments, exams, and downloadable material.
Shows how a scientific portal separates tools, courses, papers, teaching materials, workshops, and user submissions.
Strong benchmark because it explicitly packages full-semester course material with labs, homework, and exams.
Essential open-PDK reference for many SemiAgora examples.
Accessible educational path from small digital designs to real manufactured chips.
Small circuit design exercises for practicing Verilog.
Primary model-family page for BSIM-CMG, BSIM-IMG, BSIM-SOI, BSIM-BULK, and BSIM4.
Benchmark for graphical abstract service packaging and journal-format deliverables.
Rectification, consecutive-slope NDR, overlap and resonant mechanism classes, series/contact burden, sweep history, and replacement-evidence anchors.
Thermoelectric response, series-junction scaling, reference-junction correction, calibration, repeatability, drift, hysteresis, mechanical burden, cross-sensitivity, uncertainty, and traceability lineage.
Feature-scale particle transport, surface interaction, evolving etch/deposition profiles, open reproduction, software rights, commercial comparison vocabulary, and replacement-evidence planning.
CCP/ICP reference vocabulary, source/bias coupling, sheath and IED evidence, pressure/collisionality, wall and chemistry loss, radial uniformity, benchmark discipline, feature-scale handoff, and replacement evidence.
Vacuum-flow regime, throughput and inventory, conductance versus effective pumping, wall source, transient response, molecular-flow boundary, pressure and flow calibration, uncertainty, and replacement evidence.
Ion-neutral synergy, passivation, directionality, mask and selectivity, feature transport, damage, plasma metrology, endpoint evidence, open model reproduction, and replacement-evidence boundaries.
RESEARCH STUDIO POSITION
SemiAgora Research Studio should help graduate students and researchers by reproducing simulations, checking claim-evidence alignment, improving technical English, redrawing original figures, and building transparent condition cards.
Re-run, package, and explain simulations from permissible inputs. The deliverable is a transparent condition card, not a prettier fiction.
Check whether figures, captions, claims, citations, and limitations match the data and methods the author can actually defend.
Build new mechanism diagrams, waveform figures, graphical abstracts, posters, and slide visuals without copying publisher assets.
Improve clarity, structure, and reviewer-response language while preserving the author's scientific meaning and contribution.
Education
Use these to design SemiAgora lessons with lecture notes, worksheets, exams, and self-checks instead of publishing isolated posts.
A strong model for packaging a semiconductor course with syllabus, readings, lecture notes, assignments, exams, and downloadable material.
Shows how a scientific portal separates tools, courses, papers, teaching materials, workshops, and user submissions.
A practical beginner-friendly reference with searchable textbook navigation.
Industry-facing semiconductor training model with on-demand, virtual, and in-person formats.
Professional lecture stream around electron-device research and practice.
Shows how instrument vendors package hands-on semiconductor teaching around measurement workflows.
Workforce
Use these as role and skill references. Live job listings should wait until policy, expiration, and privacy workflows exist.
Official U.S. semiconductor program context with education and workforce relevance.
Useful for framing semiconductor workforce needs, immigration, and advanced-degree talent pipelines.
Existing professional job board with semiconductor-function filtering.
Useful official calendar for industry events and possible future newsletter/event roundups.
EDA Academic
These show how commercial EDA vendors package curriculum, labs, tool access, and credentials for universities.
Commercial EDA academic program for students, educators, researchers, and entrepreneurs.
Strong benchmark because it explicitly packages full-semester course material with labs, homework, and exams.
Commercial EDA program for classroom instruction and academic research.
Useful bridge between university EDA access, training, and fabrication services.
Open Silicon
These are the best bridges from SemiAgora browser labs to reproducible silicon-flow portfolios.
Core documentation for open physical-design flows.
Practical route from digital HDL to ASIC flow execution.
Essential open-PDK reference for many SemiAgora examples.
Important second open-PDK reference beside SKY130, especially for mixed-signal and open silicon examples.
Community steward for open-source silicon projects, events, and working groups.
Accessible educational path from small digital designs to real manufactured chips.
A relevant public-learning signal for turning DRC/LVS evidence into a structured SemiAgora lab.
Useful official source anchor for explaining timing reports, path delay, slack, and parasitic handoff in public-safe EDA lessons.
Official public source spine for floorplan utilization/aspect ratio, global-placement routability, routing congestion, PDN grids, IR-drop analysis, CTS, STA, and flow-variable caution vocabulary.
Practice
Use these to shape worksheet and quiz layers without building accounts or grading infrastructure too early.
Small circuit design exercises for practicing Verilog.
Online HDL edit/run/share environment for learning and quick tests.
Digital design and verification tutorial model with examples, quizzes, and interview content.
Long-running reference for Verilog basics, testbenches, memory modeling, FSMs, and quick references.
Lab Directory
Lab pages are useful for research discovery and graduate-school navigation, but only official public pages should be linked.
Primary model-family page for BSIM-CMG, BSIM-IMG, BSIM-SOI, BSIM-BULK, and BSIM4.
Example of a lab page that states projects, facilities, device types, and student/postdoc interest.
Example of a lab page connecting modeling, fabrication, characterization, publications, and recruiting signals.
Example of a university lab page that lists facilities, EDA tools, focus areas, workshops, and publications.
Research Studio
These are commercial or tool benchmarks for manuscript editing and graphical abstracts; SemiAgora should differentiate through semiconductor-specific evidence audit and simulation support.
Benchmark for professional academic editing service packaging.
Benchmark for broad manuscript and research-communication services.
Benchmark for graphical abstract service packaging and journal-format deliverables.
Useful public design guide for graphical abstract structure and communication.
Daily Picks
These link-only items came from the 2026-08-10 seed scan and remain clearly separated from SemiAgora's own reproduced evidence.
Open semiconductor TCAD solver that can inspire future reproducible device labs.
Validation-oriented materials and device simulation project with pn-diode examples.
Current research signal around PIM simulation.
Current technical-paper pointer across several semiconductor topics.
Current research signal around devices, stacking, memory, and materials.
Packaging and 3D-integration signal beyond the current device/circuit-heavy site.
Industry context for chiplet architecture and scalable compute.
Power-device signal that expands the radar beyond MOSFET and SRAM.
A broad source-discovery signal for checking SemiAgora's semiconductor coverage gaps across process, lithography, packaging, EDA, chiplets, HBM, photonics, and TCAD.
Current public topic signal for connecting post-lithography observation to downstream etch correction and yield evidence.
Official public source for treating virtual metrology as a sampling, uncertainty, drift/shift, and process-control problem instead of a black-box prediction demo.
A public custom-HBM article that helps frame HBM4/base-die partitioning, controller placement, TSV PHY, RAS telemetry, manufacturing, assembly, and final-test boundaries.
Public source for CFET vertical stacking, monolithic versus sequential integration, PPAC framing, and source/drain contact-patterning challenges.
Public source for HPSI SiC, GaN epitaxy, RF substrate, wafer-size, and semi-insulating substrate vocabulary useful for a bounded GaN-on-SiC HEMT study map.
A link-first source spine for DRAM retention, refresh, RowHammer, ECC, RAS, simulator, and reliability guardband vocabulary.
A link-first source spine for SRAM, DRAM, HBM, Flash, MRAM, FeFET/FeRAM, ReRAM, PCM, SCM, embedded NVM, CIM, and placement vocabulary.
A link-first source spine for static timing, standard-cell mapping, Liberty/SDC/SPEF vocabulary, drive strength, load, slew, area, timing repair, and report-stage literacy.
A link-first source spine for GaN dynamic on-resistance, stress/recovery windows, current collapse, pulsed I-V, double-pulse, trap memory, thermal context, and reliability evidence vocabulary.
A link-first source spine for APC, FDC, run-to-run control, equipment data acquisition, virtual metrology, dynamic sampling, feedforward handoff, and decision-governance vocabulary.
A link-first source spine for TCAD solver literacy, DOE sampling, response surfaces, Gaussian-process uncertainty, surrogate screening, validation, and optimization guardrails.
A link-first source spine for planar MOSFET, FinFET, GAAFET nanosheet, and CFET electrostatics, contacts, variability, thermal, integration, metrology, and circuit-handoff literacy.
Official report vocabulary plus three independently verified local fixtures for clock-tree, routing, extracted-RC, PDN, IR-drop, current-density, and cross-owner handoff literacy.
A pinned author-claim benchmark plus official model, synthesis, implementation, test, and measurement-uncertainty vocabulary for evidence-ladder literacy.
Official measurement-study design, repeatability, reproducibility, bias, linearity, stability, uncertainty, crossed/nested study, and discrimination vocabulary for a bounded browser replay.
Exact constants, semiconductor optoelectronics learning scope, detector and solar boundaries, FDTD replacement evidence, microring theory, and silicon electro-optic provenance for a bounded five-node packet.
Small-signal, S-parameter, reference-impedance, transmission-line, calibration, de-embedding, passivity, stability, noise, and uncertainty anchors for a bounded five-node RF packet.
Contact, interface, compact-model, extraction, metrology, circuit-PPA, benchmarking, and replacement-evidence anchors for a bounded 2D CFET packet.
Geometry, current crowding, edge and constriction evidence, photon/dark mechanisms, timing, radiometry, calibration traceability, and uncertainty anchors for a bounded SNSPD packet.
Tier assignment, oxide-semiconductor transport, contact, inter-tier connection, thermal budget, cell/subarray loading, extraction, uncertainty, and replacement-evidence anchors.
Rectification, consecutive-slope NDR, overlap and resonant mechanism classes, series/contact burden, sweep history, and replacement-evidence anchors.
Thermoelectric response, series-junction scaling, reference-junction correction, calibration, repeatability, drift, hysteresis, mechanical burden, cross-sensitivity, uncertainty, and traceability lineage.
Feature-scale particle transport, surface interaction, evolving etch/deposition profiles, open reproduction, software rights, commercial comparison vocabulary, and replacement-evidence planning.
CCP/ICP reference vocabulary, source/bias coupling, sheath and IED evidence, pressure/collisionality, wall and chemistry loss, radial uniformity, benchmark discipline, feature-scale handoff, and replacement evidence.
Vacuum-flow regime, throughput and inventory, conductance versus effective pumping, wall source, transient response, molecular-flow boundary, pressure and flow calibration, uncertainty, and replacement evidence.
Ion-neutral synergy, passivation, directionality, mask and selectivity, feature transport, damage, plasma metrology, endpoint evidence, open model reproduction, and replacement-evidence boundaries.
Cross-domain variation, measurement, device-model transfer, circuit margin, reliability, test, genealogy, yield, and publication-review boundaries.
HAR, ALE, selective etch, DRIE, strip and ash, wet etch, profile, selectivity, residue, metrology, and cross-role evidence boundaries.
PVD, CVD and PECVD, ALD and PEALD, LPCVD and furnace, epitaxy, selective deposition, ECD gap-fill, films, interfaces, metrology, and cross-role evidence boundaries.
Mask and reticle, substrate and wafering, scanner and track, ion implant, thermal processing, clean and surface, CMP, metrology, and cross-role evidence boundaries.
Endpoint sensing, inspection and metrology, chamber-state FDC, maintenance, edge and backside inspection, process-control, traceability, and cross-role evidence boundaries.
Cluster routing, facility and abatement, resource metering, operating-state attribution, emissions and allocation boundaries, traceability, EHS, assurance, and cross-role evidence review.
Bonding and interfaces, thinning and dicing, probe and test measurement, panel packaging, traceability, calibration, coverage, reliability, qualification, and cross-role evidence review.
Release provenance, route lineage, source-family discovery, access labels, and rights-boundary review.
Research-question triage, candidate source selection, source-family review, and citation metadata starter export.
WHAT THIS PAGE IS NOT
Every card points outward. SemiAgora records why a source matters, but the source owner keeps the material.
External pages are context. SemiAgora evidence still requires reproducible inputs, conditions, outputs, and limitations.
Live operations need expiration rules, privacy handling, moderation, and disclosure before they become public features.