3072 casesRC ladder rowsUNKNOWNInspect metric contract
4 contextsDesign contextsUNKNOWNInspect metric contract
4 stagesEvidence checkpointsUNKNOWNInspect metric contract
0Live server runsUNKNOWNInspect metric contract
SIMULATION / SA-EDA-RC-001
Layout RC delay evidence ladder
Layout RC -> delay
A browser CSV lab that connects layout wire length, layer class, route style, load class, and checkpoint stage to RC, delay, slew, slack-risk, and evidence-state proxies.
EXPLORE
Start with the observable.
Use this page when the simulation is the primary artifact. The linked lesson explains the concept; the linked lab keeps the visual replay surface available.
- Filter design context, route style, load class, and checkpoint stage to see how layout evidence changes before timing is claimed.
- Compare Rwire, Cwire, coupling, total load, Elmore-style delay, input slew, setup slack delta, hold slack delta, and risk proxies together.
- Use evidence state and next safe check as a paper-writing discipline: an estimate can guide a question, but it is not signoff.
- Open the model card before reusing a row in a lecture, review note, or reproducible-report backlog.
BROWSER INTERACTIVE LAB
Filter the saved CSV. Inspect matching replay rows.
No server solver is running here. The browser filters a precomputed table and redraws the plot locally.
Loading replay rowsReading the saved CSV in this browser.
elmore delay ps proxysetup slack delta ps proxyslew risk proxy
Each metric is normalized independently for shape inspection. Vertical positions do not compare magnitude across metrics.
n/aelmore delay ps proxy
n/asetup slack delta ps proxy
n/aslew risk proxy
Change one or more controls to find a saved row. No unrelated CSV value is substituted.
| case id | design context | path topology | routing layer class | route style | fanout load class | checkpoint stage | wire length um proxy | r wire ohm proxy | c wire ff proxy | coupling ff proxy | total load ff proxy | input slew ps proxy | elmore delay ps proxy | setup slack delta ps proxy | hold slack delta ps proxy | slew risk proxy | evidence state | next safe check |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Loading saved replay rows... | ||||||||||||||||||
RUN CARD
Conditions before conclusions.
The browser filters saved CSV rows and redraws local plots. It does not run OpenROAD, OpenLane, OpenSTA, Magic, Netgen, ngspice, SPICE, TCAD, or a server-side compile flow.
Primary knobs
- design_context: inverter_chain, sram_wordline_driver_proxy, sram_bitline_sense_proxy, counter_clock_spine
- path_topology: short_local, cell_row, macro_edge, detoured_channel
- routing_layer_class: local_m1_like, intermediate_m2_m3_like, upper_m4_like
- route_style: minimum_width, widened, shielded_neighbor, congestion_detour
- fanout_load_class: fo1_logic, fo4_logic, sram_peripheral, clock_or_reset_fanout
- checkpoint_stage: schematic_load_only, floorplan_hpwl_proxy, global_route_estimate, pex_timing_proxy
Saved outputs
- wire length proxy
- Rwire proxy
- Cwire proxy
- coupling proxy
- total load proxy
- input slew proxy
- Elmore-style delay proxy
- setup and hold slack delta proxies
- buffer count hint
- slew and crosstalk risk proxies
- evidence state
- next safe check
EXPORT
Download the public artifacts.
These exports are the supported public files for review. PDK files and restricted third-party material are not redistributed.
Layout RC replay CSV
/data/layout-rc-delay-evidence-ladder-v79.csv
Open file ->Web result JSON
/data/layout-rc-delay-evidence-ladder-web-v1.json
Open file ->Model card
/data/layout-rc-delay-evidence-ladder-model-card-v1.md
Open file ->METHODS
How the number was made.
Methods are written for citation discipline: the extraction rule matters as much as the plotted value.
Generate a 3072-row factorial teaching table over design context, topology, layer class, route style, load class, and checkpoint stage.
Keep this method attached when reusing the figure or metric.
Compute Rwire, Cwire, coupling, total load, Elmore-style delay, input slew, setup/hold slack deltas, buffer hint, risk proxies, confidence, and evidence state.
Keep this method attached when reusing the figure or metric.
Use official public source anchors for vocabulary and flow framing only; all visible rows, formulas, labels, and limitations are original SemiAgora teaching content.
Keep this method attached when reusing the figure or metric.
LIMITS
What this page does not claim.
The MVP is useful because the limits are visible. These statements prevent a teaching simulation from being cited as silicon evidence.
The RC and timing numbers are educational proxies and are not calibrated to any foundry, design kit, extracted deck, or STA corner.
Carry this boundary into any derivative note, paper draft, or slide.
Layer classes are abstract labels, not SKY130 rule values, routing recommendations, design rules, or process guidance.
Carry this boundary into any derivative note, paper draft, or slide.
A real report package needs owned design files, exact tool versions, PDK/license authority, extraction settings, Liberty/SPEF/SDC provenance, and design-owner review.
Carry this boundary into any derivative note, paper draft, or slide.
No live server solver, uploaded design, equipment-control action, or arbitrary netlist execution is enabled.
Carry this boundary into any derivative note, paper draft, or slide.
This lab teaches evidence order; it cannot decide buffer insertion, route changes, timing closure, signoff, tapeout, or production release.
Carry this boundary into any derivative note, paper draft, or slide.
EVIDENCE
Trace the claim back to artifacts.
The evidence route remains the catalog-level browser; this page is the simulation-level reading card.
The CSV preserves every design context, topology, layer class, route style, load class, checkpoint stage, and evidence metric used by the browser lab.
SA-EDA-RC-001
The JSON stores row counts, public boundaries, source anchors, methods, limitations, chain views, and highest-risk examples.
SA-EDA-RC-001
The EDA/Layout lane now has a layout RC -> delay surface beside PV checkpoint replay, STA slack replay, and OpenROAD starter report parsing.
SA-EDA-RC-001
The public page teaches report literacy only: no uploaded design, no real tool flow, no PDK collateral, and no timing-closure claim.
SA-EDA-RC-001
Source spine
These links anchor the public teaching model. They do not convert the replay into a qualified process recipe or signoff result.
OpenROAD documentationOfficial project documentation anchor for digital place-and-route, parasitic extraction, and STA vocabulary; no tool run is exposed on the public page.OpenROAD Flow ScriptsOfficial flow repository anchor for future reproducible report packages; no repository code, report, or PDK collateral is mirrored.OpenLane 2 documentationPublic flow documentation anchor for timing-closure vocabulary and report-literacy planning.OpenSTA repositoryStatic timing analyzer source anchor for Liberty, SDC, SPEF, timing-path, and slack vocabulary.SkyWater SKY130 PDK documentationOpen-PDK documentation anchor; no PDK files, rule decks, extracted netlists, or models are redistributed.Magic VLSIOfficial Magic page anchoring public layout/DRC/extraction vocabulary.NetgenOfficial Netgen page anchoring LVS comparison vocabulary.
Public execution boundary
No server-side live ngspice execution, uploads, accounts, payments, comments, newsletter signup, or job/event submissions are active on this page.