Start with design context, topology, layer class, route style, load class, and checkpoint stage.
Open the run card to inspect the saved rows, methods, limits, and export files behind this step.
Inspect run card ->LESSON PACKET / SA-EDA-RC-001
Turn layout RC into delay evidence.
EDA / Layout
The useful EDA lesson is not a button sequence. It is how wire length, layer class, route style, load, and checkpoint stage become RC, delay, slew, slack-risk, and evidence-state proxies with the PDK and signoff boundary still attached.
EVIDENCE SEQUENCE
What the learner should inspect first.
This surface connects the daily-scan source signal to an original SemiAgora simulation object without copying source text, code, figures, PDK files, or process recipes.
Compare Rwire, Cwire, coupling, total load, delay, slew, setup slack, hold slack, and risk proxies together.
Open the run card to inspect the saved rows, methods, limits, and export files behind this step.
Inspect run card ->Read evidence state and next safe check before turning a report-like row into a claim.
Open the run card to inspect the saved rows, methods, limits, and export files behind this step.
Inspect run card ->METHODS
Precomputed model contract.
The goal is useful study scaffolding and paper-planning discipline, not calibrated production evidence.
Original synthetic layout RC and timing table based on public EDA vocabulary.
The simulation object keeps the same statement beside downloadable JSON and CSV evidence.
No PDK file, rule deck, Liberty, SPEF, SDC, GDS, DEF, report, or OpenROAD/OpenLane project is copied.
The simulation object keeps the same statement beside downloadable JSON and CSV evidence.
The browser filters saved CSV rows and exposes the model card with no-live-flow boundaries.
The simulation object keeps the same statement beside downloadable JSON and CSV evidence.
LIMITS
Useful, but deliberately bounded.
No account, upload, payment, comment, newsletter, live solver, facility workflow, or product-release surface is enabled.
No calibrated extraction, timing closure, macro timing, SRAM compiler, tapeout, foundry, product, or signoff claim.
Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.
Layer classes and route styles are teaching proxies, not design rules or routing guidance.
Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.
Real work needs owned design data, exact tool versions, PDK/license authority, Liberty/SPEF/SDC provenance, and design-owner review.
Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.
SOURCE ANCHOR
Link-only public source spine.
SemiAgora uses the source as a signal and citation anchor, then writes original summaries and original toy data with explicit limitations.
OpenROAD / OpenSTA / OpenLane official source spine
https://openroad.readthedocs.io/en/latest/
Open source ->