Explain why an SRAM write is a contest between the access path and the cross-coupled latch.
Use the lab and worksheet to check whether the claim is understood rather than memorized.
LESSON PACKET / SRAM WRITE BOUNDARY
A write is a fight.
Assist moves the boundary.
Wordline amplitude, write assist, and dynamic pass/fail evidence. This page packages the lecture notes, evidence contract, worksheet, citations, and correction path around one executed lab.
LEARNING OUTCOMES
What the learner should be able to defend.
MIT OCW-style lesson packaging works because it bundles objectives, notes, assignments, evidence, and source boundaries. This packet uses the same structure but keeps SemiAgora's simulation evidence visible.
Distinguish a dynamic write-success boundary from static write-margin metrics such as WSNM.
Use the lab and worksheet to check whether the claim is understood rather than memorized.
Read a two-axis shmoo using wordline amplitude and ideal cell-VDD write assist.
Use the lab and worksheet to check whether the claim is understood rather than memorized.
State the metric contract, success criterion, and limitations before reusing the result.
Use the lab and worksheet to check whether the claim is understood rather than memorized.
SRAM MASTERY MAP
Master SRAM as a spine, then branch into other memories.
Books and papers are used as coverage checks, not copied source material. SemiAgora should implement the underlying SRAM phenomena with original explanations, figures, and reproducible condition cards.
Cell operation and stability
Read disturb, static noise margin, and dynamic write boundary are already connected to executed labs.
Open path ->Sizing, assist, and variation
Next SRAM labs should isolate access ratio, pull-up ratio, WL/BL assist, low-VDD failure, PVT, and mismatch.
Open path ->Array and peripheral behavior
Sense amplifier, write driver, column mux, bitline RC, redundancy, ECC, and compiler-spec reading become the expansion layer.
Open path ->LECTURE NOTES
The causal chain.
Start from the stored state, open the access path, weaken the latch with assist, and apply the explicit pass/fail rule. Do not read the plot without the metric contract.
The cell starts latched.
Q begins at 0 and QB begins at 1. The write target is the opposite state: Q=1 and QB=0.
The wordline opens the write path.
Raising WL turns on the access transistors. Higher WL increases the ability of the bitlines to disturb and flip the internal nodes.
Lower cell VDD weakens the latch.
During the write pulse, ideal local cell-VDD collapse reduces the latch strength. The write path can then win at a lower WL amplitude.
The pass/fail rule is explicit.
At 7.5 ns after supply restoration, the case passes only if Q is above 1.35 V and QB is below 0.45 V.
EVIDENCE CONTRACT
Read the number with its condition.
SKY130_SRAM_WRITE_BOUNDARY_001 uses SKY130A TT, 27 C. The metric is named dynamic write-success boundary, and the pass/fail threshold is part of the result.
Assist VDDMinimum WLPassing casesBoundary
Pass condition
at 7.5 ns after supply restoration: Q > 1.35 V and QB < 0.45 V
DOWNLOADS
Make the packet inspectable.
These files support review and reproduction. PDK files are not included; users must install and license the PDK separately.
sky130-sram-write-boundary-web-v1.json
Published evidence or reproduction support file for this packet.
Open file ->write-boundary-summary.csv
Published evidence or reproduction support file for this packet.
Open file ->run_write_shmoo.py
Published evidence or reproduction support file for this packet.
Open file ->verify_write_shmoo.py
Published evidence or reproduction support file for this packet.
Open file ->reproduce_write_shmoo.sh
Published evidence or reproduction support file for this packet.
Open file ->SOURCE_NOTES_WRITE.md
Published evidence or reproduction support file for this packet.
Open file ->SOURCES
Citations motivate context, not hidden copying.
The papers and tool docs are used as source context. The shmoo grid, waveform data, scripts, and web presentation are original SemiAgora artifacts.
Seevinck, List, and Lohstroh, Static-noise margin analysis of MOS SRAM cells
Motivates SRAM stability context; this packet does not reproduce the paper's figures.
Open source ->Grossar, Stucchi, Maex, and Dehaene, Read Stability and Write-Ability Analysis of SRAM Cells
Motivates write-ability framing; the shmoo grid is original SemiAgora execution.
Open source ->Pilo et al., SRAM design with read and write-assist circuits
Motivates assist-circuit context; this packet uses an ideal local VDD assist.
Open source ->SkyWater Open Source PDK documentation
PDK and model context; PDK files are not redistributed by SemiAgora.
Open source ->ngspice documentation
Simulator documentation; execution details remain in SemiAgora's package files.
Open source ->LIMITATIONS
What this lesson does not claim.
The visible boundary is part of the lesson. Removing it would make the evidence easier to misuse.
Pre-layout schematic compact-model simulation at one TT/27 C condition.
Use this sentence when citing or adapting the lesson.
No mismatch, PVT sweep, extracted parasitics, package effects, sense amplifier, driver impedance, array coupling, or half-selected cells.
Use this sentence when citing or adapting the lesson.
The cell-VDD assist is ideal and local; it is not a complete assist-circuit implementation.
Use this sentence when citing or adapting the lesson.
The metric is dynamic write-success boundary, not WSNM, BLVM, WLVM, N-curve margin, write-trip voltage, or a measured silicon value.
Use this sentence when citing or adapting the lesson.