Integration / Memory / EvidenceLive
Emerging device, memory & integration atlas
MRAM, FeFET/HZO, IGZO, 2D CFET, p-GaN contacts, GaN HEMT, and 3D integration across five disjoint evidence dimensions, held gates, contradictions, and replacement slots
TOUCH LABS
Pick one knob.
See what moves.
Start with the six-family etch-depth atlas: choose HAR, ALE, selective etch, DRIE, strip and ash, or wet etch, then load one validated CSV and keep profile, selectivity, transport, mask, residue, metrology, role, and replacement-evidence boundaries visible. Continue into RIE mechanism, vacuum and gas delivery, plasma source and sheath state, particle Monte Carlo topography, process-device-yield integration, metrology, devices, memory, circuits, reliability, and verification.
Device / Modeling / EvidenceDevice modeling & normalization workbench9 metric contracts / 27 fixtures / 10 refusals / 12 sourcesMemory / SRAM / VariabilitySRAM variation and corner coverage2400 synthetic rows / 8 fixtures / 8 sourcesProcess / Metrology / VariabilityLER/LWR variability lab256 synthetic samples / 8 fixtures / 6 sourcesProcess / Equipment / MetrologyEtch depth and selectivity evidence atlas41472 rows / 20736 physical configurations / 120 sourcesIntegration / YieldProcess-device-yield integration evidence map5760 rows / 2880 physical configurations / 20 sourcesProcess / EquipmentReactive-ion etch mechanism evidence map6912 rows / 3456 physical configurations / 18 sourcesEquipment / ProcessVacuum and gas-delivery inventory evidence map10368 rows / 5184 physical configurations / 14 sourcesEquipment / ProcessCCP versus ICP chamber-state evidence map6144 rows / 3072 physical configurations / 14 sourcesProcess / EquipmentParticle Monte Carlo feature topography evidence map6144 rows / 192 physical configurations / 8 sourcesSensor / MetrologyThermoelectric temperature-sensor calibration evidence map6144 rows / 384 configurations / 7 nodesDevice / Metrology2D heterojunction NDR evidence map6144 rows / 192 sweep pairs / 9 nodesMemory / DeviceM3D Si/oxide-semiconductor SRAM evidence ladder6144 deterministic rows / 9 nodesSensor / MetrologySuperconducting photon-detector evidence map5184 deterministic rows / 6 nodesRF DeviceRF S-parameter and de-embedding evidence replay6048 deterministic rows / 5 nodesPhotonicsSemiconductor photonics causal chain4536 deterministic rows / 5 nodesDeviceCFET contact/interconnect parasitic map1728 CFET rowsDeviceMOSFET, FinFET, GAAFET, and CFET architecture comparison4096 comparison rowsLayoutCTS, routing, and IR-drop report handoff4096 handoff rowsLayoutOpen-silicon model-to-measurement evidence4096 evidence rows / 0 real measurementsMetrologyGauge R&R and measurement-system analysis4096 measurement-system rows / 15 gatesMemoryHBM base-die partition map1296 HBM partition rowsMetrologySmall-data virtual metrology replay2880 VM decision rowsProcessPlasma etch UQ surrogate replay27 heteroscedastic UQ rowsLayoutPhysical verification evidence ladder192 PV checkpoint rowsMemoryMRAM fundamentals replay18 MRAM triangle rowsPackagingHybrid bonding mechanical readiness27 readiness rowsMemorySRAM dynamic write boundary24 SKY130 transientsMemoryDRAM HBM emerging memory replay18 memory/eNVM cardsDeviceAdvanced device architecture2 advanced-device cardsDigitalDigital timing primitives1 timing primitive cardMemorySRAM memory depth replay5 memory-depth cardsMemorySRAM column MUX and I/O replay864 verified ngspice rowsMemory6T SRAM read operation3 SKY130 transientsMemoryStatic noise marginngspice datasetDigitalSRAM timing and controllerCross-checked RTLDigitalMarch C- SRAM BISTExecuted RTLDigitalSECDED memory ECC92 executed casesMemoryDifferential bitline sensingExecuted ngspiceMemoryDRAM retention and refreshExecuted ngspice
REPRODUCIBLE LABS
Change one condition.
Trace every consequence.
Models are labeled by fidelity. Every result exposes its assumptions, execution method, validation state, and downloadable evidence.
Device / Modeling / EvidenceLive
Device modeling & normalization workbench
Planar, fin, and nanosheet geometry; total and width-normalized Ioff; gm/Id operating conditions; synthetic TLM; contact drop; residual splits; corner versus Monte Carlo; and five disjoint SPICE layers
Metrology / Variability / UQLive
Variability, metrology & UQ workbench
Eight same-contract uncertainty budgets across LER/LWR, PSD, aperture, finite sampling, SRAM hierarchy, plasma etch, Gauge R&R, and hybrid bonding with explicit refusal states
Circuit / Numerical evidenceLive
SPICE convergence evidence
Compare solver, numerical, model, metric, and signoff states across timestep, tolerance, initial-condition, saved-signal, and measurement-definition cases without treating convergence as validity
Memory / SRAM / VariabilityLive
SRAM variation and corner coverage
Known-ground-truth condition, lot, wafer, site, and replicate hierarchy with covariance-aware variance closure, missingness coverage, uncertainty denominators, and fixed-condition boundaries
Process / Metrology / VariabilityLive
LER/LWR variability lab
Seeded paired edge traces, exact left-right correlation, extraction bandwidth, local-CD aperture, histogram conservation, and bounded device-to-SRAM sensitivity proxies
Process / Equipment / MetrologyLive
Etch depth and selectivity evidence atlas
Choose HAR, ALE, selective etch, DRIE, strip and ash, or wet etch; load one validated family CSV; inspect profile, selectivity, residue, surface, metrology, exact-ledger, and role-gate evidence
Integration / YieldLive
Process-device-yield integration evidence map
Variation families, device and circuit evidence, reliability and yield context, genealogy, four role views, three exact ledgers, upstream packet postures, and the v120 human-review gate
Process / EquipmentLive
Reactive-ion etch mechanism evidence map
Ion drive, neutral reactivity, passivation, directionality, mask resilience, feature access, six mechanism regimes, exact ledgers, role gates, and the bounded feature-profile handoff
Equipment / ProcessLive
Vacuum and gas-delivery inventory evidence map
Flow-model regime, admitted load, wall release, conductance, nominal and effective pumping, chamber and foreline inventory, settling, distribution, exact ledgers, role gates, and the bounded plasma handoff
Equipment / ProcessLive
CCP versus ICP chamber-state evidence map
Bounded architecture, drive, pressure, bias, gas response, wall loss, matching, sheath, ion/neutral delivery, energy-angle breadth, radial state, exact ledgers, role gates, feature bridge, and replacement evidence
Process / EquipmentLive
Particle Monte Carlo feature topography evidence map
Directional RIE and sputter deposition across source, species, surface, reflection, secondary transport, exact geometry, conservation, role views, and replacement gates
Sensor / MetrologyLive
Thermoelectric temperature-sensor calibration evidence map
Series-junction scaling, reference-junction correction, drift, mechanical hysteresis, cross-sensitivity, residual, uncertainty, traceability, and replacement gates
Device / MetrologyLive
2D heterojunction NDR evidence map
Bias, gate state, band alignment, broadening, background transport, contact pressure, sweep direction, trap memory, and stable negative-slope evidence gates
DeviceLive
PN junction bias
Potential, carriers, and solved current-voltage response
DeviceLive
2D MOSFET transfer
Gate control, two drain biases, current, and solved surface inversion
DeviceLive
MOS capacitor C-V
Gate bias, surface carriers, quasi-static C-V, and high-frequency boundary
DeviceLive
Advanced device architecture
FinFET fin-count PPA, GAA nanosheet electrostatics, and variability boundaries
DeviceLive
CFET contact/interconnect parasitic map
Stacked n/p devices, MOL contacts, vias, local interconnect, thermal coupling, delay, energy, and integration risk
Power DeviceLive
GaN-on-SiC HEMT substrate chain
Semi-insulating SiC, GaN buffer traps, HEMT mode, package thermal path, dynamic Ron, and reliability gates
Power DeviceLive
GaN dynamic-Ron and trap-memory replay
Stress class, drain bias, recovery window, trap memory, current collapse, thermal risk, and method caution
DeviceLive
TCAD DOE and surrogate optimization replay
Device context, design lever, DOE plan, surrogate uncertainty, extrapolation risk, mesh stability, calibration anchor, and decision gate
DeviceLive
MOSFET, FinFET, GAAFET, and CFET architecture comparison
Electrostatic control, footprint, contacts, capacitance, variability, thermal coupling, integration risk, evidence maturity, and circuit handoff
RF DeviceLive
RF S-parameter and de-embedding evidence replay
Complex intrinsic and fixture-embedded S-parameters, reference impedance, correction classes, residual error, fixture passivity, linear stability, fT/fmax, RF noise, and replacement evidence
PhotonicsLive
Semiconductor photonics causal chain
Photon energy, LED and laser boundaries, ideal detector responsivity, all-pass ring transfer, MZI phase, and replacement-evidence gates
Sensor / MetrologyLive
Superconducting photon-detector evidence map
Geometry, normalized current distribution, edge and constriction state, photon or dark context, mechanism ambiguity, timing/radiometry lineage, uncertainty, and replacement gates
Memory / DeviceLive
M3D Si/oxide-semiconductor SRAM evidence ladder
Tier assignment, oxide access transport, contacts, inter-tier links, WL/BL loading, thermal budget, extraction maturity, cell/subarray sensitivities, contradictions, and replacement evidence
CircuitLive
CMOS inverter transfer
Input, output, gain, and sampled noise margins
CircuitLive
Ring oscillator
Stage count, capacitive load, frequency, delay, and switching power
CircuitLive
Analog circuit primitives
Current mirror compliance, output resistance, sense regeneration, and decision margin
DigitalLive
Digital timing primitives
FO4 delay, VDD, temperature, energy, leakage, and EDP timing vocabulary
MemoryLive
6T SRAM read operation
Precharge, wordline, differential bitlines, read disturb, and load-dependent delay
MemoryLive
Static noise margin
Butterfly curve, maximum square, and hold/read comparison
MemoryLive
SRAM dynamic write boundary
Wordline amplitude, cell-VDD assist, pass/fail shmoo, and write waveform
MemoryLive
SRAM column MUX and I/O replay
Mux ratio, shared sense load, transfer efficiency, write off-state, and output timing
MemoryLive
SRAM memory depth replay
Sense margin, column I/O, read-disturb sizing, assist taxonomy, and cache behavior evidence layers
MemoryLive
DRAM HBM emerging memory replay
DRAM/HBM bank behavior, retention, RowHammer, NAND, 3D NAND, PCM, ReRAM, FeFET, MRAM, hierarchy, and CIM tradeoffs
MemoryLive
HBM base-die partition map
DRAM stack, base die, TSV, interposer, PHY, controller, thermal, bandwidth, capacity, and yield tradeoffs
MemoryLive
DRAM refresh, RowHammer, and ECC guardband
Retention tails, temperature, refresh tax, activation pressure, ECC/scrub coverage, thermal stress, residual risk, and next evidence checks
MemoryLive
Emerging memory placement and reliability map
SRAM, DRAM, HBM, NAND, MRAM, FeFET, ReRAM, PCM, SCM, embedded NVM, eDRAM, and CIM placement evidence
MemoryLive
MRAM fundamentals replay
Switch probability, write energy, read margin, retention proxy, and disturb risk
LayoutLive
SKY130 physical verification
Actual GDS layers, DRC, LVS, PEX, and pre/post timing
LayoutLive
Physical verification evidence ladder
DRC/LVS/PEX/timing checkpoints, evidence confidence, fix-risk proxy, and safe evidence checks
LayoutLive
Layout RC delay evidence ladder
Wire length, layer class, route style, fanout load, checkpoint stage, RC, slew, and slack-risk proxies
LayoutLive
Floorplan congestion, IR-drop, and clock spine
Utilization, macro channels, PDN strategy, routing congestion, IR-drop, CTS pressure, skew, and timing-risk gates
LayoutLive
Standard-cell delay, area, and pin-cap reports
Drive strength, input slew, output load, pin cap, setup/hold slack, max-cap/slew risk, and report-stage evidence
LayoutLive
CTS, routing, and IR-drop report handoff
Clock skew/latency, route overflow/completion, extracted RC, IR/current-density pressure, report mismatch, replacement slots, and owner review
LayoutLive
Open-silicon model-to-measurement evidence
Model assumptions, characterization, routed reports, test structures, measurement state, discrepancy, uncertainty, provenance, and claim maturity
MetrologyLive
Gauge R&R and measurement-system analysis
Crossed/nested design, part spread, repeatability, operator/tool/interaction reproducibility, bias, linearity, stability, resolution, uncertainty, and discrimination
ProcessLive
Thin-film deposition replay
Sputter uniformity, PVD step coverage, evaporation line-of-sight, and ALD growth-per-cycle saturation
ProcessLive
Process fundamentals replay
Oxidation, lithography, plasma etch UQ, CMP, implant, and anneal evidence cards
ProcessLive
Plasma etch UQ surrogate replay
Wafer zone, changing uncertainty, CD bias, selectivity, and optimizer caution
ProcessLive
Process metrology replay
Ellipsometry, sheet resistance, TLM, CD/overlay, SPC, DOE, and lithography-to-etch feedforward evidence cards
MetrologyLive
Small-data virtual metrology replay
Sparse physical metrology, model uncertainty, drift, guardband, Cpk proxy, escape risk, and sample-more decisions
ProcessLive
APC, FDC, and feedforward decision replay
Signal quality, FDC state, VM uncertainty, sampling coverage, feedforward handoff, false-alarm risk, wafer-at-risk, and role review
ProcessLive
Surface treatment replay
O2 plasma, O3 ozone, contact angle, residue proxy, and recovery boundaries
ProcessLive
Thermal annealing replay
RTA activation, thermal budget, implant recovery, TED, and silicide contact windows
ProcessLive
Wet clean surface prep replay
Contamination removal, native oxide, HMDS adhesion, and clean-sequence evidence queue
EquipmentLive
Equipment facilities replay
Cleanroom particle budget, vacuum pumpdown, tool availability, and utilities load cards
PackagingLive
Packaging test reliability replay
Package parasitics, thermal stack, wafer sort guardband, and reliability stress cards
PackagingLive
Hybrid bonding mechanical readiness
Roughness, stiffness spread, particle state, metrology sigma, and readiness bands
DigitalLive
SRAM timing and controller
Read/write protocol, assertions, and verified timing trace
DigitalLive
March C- SRAM BIST
80-access fault test with SA0/SA1 injection and cycle replay
DigitalLive
SECDED memory ECC
Exhaustive one- and two-bit codeword fault injection
MemoryLive
DRAM retention and refresh
Storage-capacitor leakage, sensing boundary, and refresh margin
MemoryLive
Differential bitline sensing
Cell current, bitline capacitance, and sense-enable timing
LayoutLive
Distributed interconnect delay
Lumped versus 3/5-section RC delay and Elmore approximation
LayoutLive
Interconnect crosstalk
Coupling capacitance, victim peak noise, and recovery time
LayoutLive
Power rail IR drop
Load current, rail resistance, voltage gradient, and endpoint supply loss