Start with architecture profile: lateral GAA, forksheet, monolithic CFET, or sequential CFET.
Open the run card to inspect the saved rows, methods, limits, and export files behind this step.
Inspect run card ->DEVICE REPLAY LAB / SA-DEV-CFET-001
Stacked devices still need contact evidence.
Device
CFET is not just a smaller cell picture. The useful question is whether vertical stacking survives contact resistance, local interconnect capacitance, via alignment, thermal coupling, and integration risk once a circuit context is attached.
EVIDENCE SEQUENCE
What the learner should inspect first.
This surface connects the daily-scan source signal to an original SemiAgora simulation object without copying source text, code, figures, PDK files, or process recipes.
Add contact scheme, local interconnect pitch, via strategy, thermal context, and circuit context before reading any density score.
Open the run card to inspect the saved rows, methods, limits, and export files behind this step.
Inspect run card ->Use the decision gate to decide whether the row is contact-limited, via-limited, thermal-limited, integration-limited, or a promising density tradeoff.
Open the run card to inspect the saved rows, methods, limits, and export files behind this step.
Inspect run card ->METHODS
Precomputed model contract.
The goal is useful study scaffolding and paper-planning discipline, not calibrated production evidence.
Original synthetic CFET pathfinding table based on public imec, IRDS, and Synopsys vocabulary.
The simulation object keeps the same statement beside downloadable JSON and CSV evidence.
No PDK, TCAD deck, device stack recipe, layout, extraction tech file, or measured silicon data is copied.
The simulation object keeps the same statement beside downloadable JSON and CSV evidence.
The browser filters saved CSV rows and exposes the model card with no-live-solver boundaries.
The simulation object keeps the same statement beside downloadable JSON and CSV evidence.
LIMITS
Useful, but deliberately bounded.
No account, upload, payment, comment, newsletter, live solver, facility workflow, or product-release surface is enabled.
No calibrated CFET compact model, 3D PEX result, foundry node rule, process integration flow, or measured silicon claim.
Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.
No live TCAD, PEX, SPICE, field solver, uploaded layout, account, payment, comment, newsletter signup, job/event workflow, or public service intake.
Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.
Real work needs owned process assumptions, contact extraction, variation modeling, thermal evidence, circuit context, and design-owner review.
Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.
SOURCE ANCHOR
Link-only public source spine.
SemiAgora uses the source as a signal and citation anchor, then writes original summaries and original toy data with explicit limitations.
imec CFET logic roadmap
https://www.imec-int.com/en/articles/imec-puts-complementary-fet-cfet-logic-technology-roadmap
Open source ->