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SIMULATION / SA-DEV-CFET-001

CFET contact/interconnect parasitic map
CFET Parasitics

A browser CSV lab for advanced-device pathfinding: compare lateral GAA, forksheet, monolithic CFET, and sequential CFET choices against contact resistance, local interconnect capacitance, via alignment, thermal coupling, parasitic delay, energy, integration risk, and density gain before making a PPAC claim.

sectionExploresectionRun CardsectionExportsectionMethodssectionLimitssectionEvidence

EXPLORE

Start with the observable.

Use this page when the simulation is the primary artifact. The linked lesson explains the concept; the linked lab keeps the visual replay surface available.

guided exploration
  • Compare lateral GAA reference, forksheet transition, monolithic CFET, and sequential CFET cases before naming an architecture winner.
  • Filter contact scheme, local interconnect pitch, via strategy, thermal context, and circuit context to see which risk owns the decision gate.
  • Watch density gain, contact resistance, capacitance, parasitic delay, energy, integration risk, and PPA proxy move together.
  • Use device, process integration, circuit, and layout/extraction views so a density benefit does not become an unsupported product claim.
Open visual lab ->Open lesson ->

BROWSER INTERACTIVE LAB

Filter the saved CSV. Inspect matching replay rows.

No server solver is running here. The browser filters a precomputed table and redraws the plot locally.

loading matching rows / x: architecture
Loading replay rowsReading the saved CSV in this browser.
ppa score proxydensity gain proxycontact resistance indexparasitic delay indexintegration risk proxy

Each metric is normalized independently for shape inspection. Vertical positions do not compare magnitude across metrics.

no matching replay row

n/appa score proxy

n/adensity gain proxy

n/acontact resistance index

n/aparasitic delay index

n/aintegration risk proxy

Change one or more controls to find a saved row. No unrelated CSV value is substituted.

case idarchitecturecontact schemeinterconnect pitchvia strategycircuit contextdensity gain proxycontact resistance indexparasitic delay indexppa score proxydecision gatenext safe check
Loading saved replay rows...

RUN CARD

Conditions before conclusions.

The browser filters saved CSV rows. It does not run live TCAD, PEX, SPICE, field solving, layout extraction, foundry decks, uploaded designs, or measured-silicon fitting.

precomputed-browser-csv-replay

Primary knobs

  • architecture profile
  • contact scheme
  • local interconnect pitch
  • via strategy
  • thermal context
  • circuit context
outputs

Saved outputs

  • density gain proxy
  • drive per footprint proxy
  • contact resistance index
  • local interconnect capacitance index
  • via alignment risk
  • parasitic delay index
  • energy index
  • integration risk proxy
  • decision gate

EXPORT

Download the public artifacts.

These exports are the supported public files for review. PDK files and restricted third-party material are not redistributed.

download

CFET parasitic replay CSV

/data/cfet-contact-interconnect-parasitic-map-v82.csv

Open file ->
download

Typed web JSON

/data/cfet-contact-interconnect-parasitic-map-web-v1.json

Open file ->
download

Model card

/data/cfet-contact-interconnect-parasitic-map-model-card-v1.md

Open file ->

METHODS

How the number was made.

Methods are written for citation discipline: the extraction rule matters as much as the plotted value.

method

Generate a Cartesian synthetic sweep across architecture, contact, interconnect, via, thermal, and circuit-context factors.

Keep this method attached when reusing the figure or metric.

method

Normalize public CFET, MOL, BEOL, backside-power, and PEX vocabulary into proxy scores for density, contact resistance, capacitance, delay, energy, thermal, and integration review.

Keep this method attached when reusing the figure or metric.

method

Apply decision gates that prioritize contact, via, thermal, and integration review before any promising-density label.

Keep this method attached when reusing the figure or metric.

method

Store the CSV, typed JSON, model card, and source boundary under the public data folder and experiment folder.

Keep this method attached when reusing the figure or metric.

LIMITS

What this page does not claim.

The MVP is useful because the limits are visible. These statements prevent a teaching simulation from being cited as silicon evidence.

non-claim

No foundry PDK, TCAD deck, standard-cell layout, CFET process flow, device stack recipe, 3D PEX result, extraction tech file, or measured silicon data is included.

Carry this boundary into any derivative note, paper draft, or slide.

non-claim

No live server TCAD, PEX, SPICE, field solver, uploaded design, account, payment, comment, newsletter signup, job/event submission, or public service intake is active.

Carry this boundary into any derivative note, paper draft, or slide.

non-claim

No node ranking, product readiness, timing signoff, density guarantee, reliability qualification, foundry roadmap claim, or process integration approval is made.

Carry this boundary into any derivative note, paper draft, or slide.

non-claim

Rows are normalized synthetic teaching proxies and require rights-cleared replacement evidence before stronger engineering reuse.

Carry this boundary into any derivative note, paper draft, or slide.

EVIDENCE

Trace the claim back to artifacts.

The evidence route remains the catalog-level browser; this page is the simulation-level reading card.

evidence note

CSV replay with 1728 rows and explicit contact, via, thermal, integration, and PPA decision gates.

SA-DEV-CFET-001

evidence note

Typed JSON summary with role views, source anchors, methods, limits, and public boundary.

SA-DEV-CFET-001

evidence note

Model card saved beside the public dataset and experiment record.

SA-DEV-CFET-001

evidence note

Source spine uses public links only and does not copy restricted vendor, roadmap, PDK, paper, or silicon data.

SA-DEV-CFET-001

Source spine

These links anchor the public teaching model. They do not convert the replay into a qualified process recipe or signoff result.

imec CFET logic roadmapPublic source for CFET as vertically stacked nMOS/pMOS, monolithic and sequential schemes, PPAC framing, and contact-patterning challenge vocabulary.imec CMOS scaling roadmapPublic source for FEOL/MOL/BEOL, contact resistance, local interconnect, via, BPR, and routing-congestion vocabulary.imec nanosheet to forksheet to CFETPublic source for CFET two-level local-interconnect and cell-area/routability teaching language.IRDS More Moore 2022Roadmap source for drive-per-footprint, parasitics, contact engineering, device stacking, and PPAC tradeoff framing.Synopsys GAA and backside powerPublic source for GAA context and backside power distribution as a routing and resistance relief concept.Synopsys CFET parasitic variation interviewPublic source for CFET parasitic variation, MOL/interconnect variation, and early PPA modeling language.Synopsys parasitic extraction glossaryPublic source defining FEOL, MEOL/contact, and BEOL/interconnect parasitics and extraction boundaries.

Public execution boundary

No server-side live ngspice execution, uploads, accounts, payments, comments, newsletter signup, or job/event submissions are active on this page.