Start with cell archetype, drive strength, input slew, output load, report stage, and optimization goal before reading slack.
Open the run card to inspect the saved rows, methods, limits, and export files behind this step.
Inspect run card ->EDA REPLAY LAB / SA-EDA-STDCELL-001
A timing report row is a compact engineering argument.
EDA / Layout
Standard-cell work is not only choosing a bigger gate. A useful report keeps drive strength, pin cap, load, input slew, output slew, area, setup slack, hold slack, report stage, and public boundary together.
EVIDENCE SEQUENCE
What the learner should inspect first.
This surface connects the daily-scan source signal to an original SemiAgora simulation object without copying source text, code, figures, PDK files, or process recipes.
Compare pin capacitance, load, fanout, delay, output slew, setup slack, hold slack, area pressure, and max-cap/max-slew risk together.
Open the run card to inspect the saved rows, methods, limits, and export files behind this step.
Inspect run card ->Use the decision gate to decide whether the next safe check is setup review, hold review, max-cap/slew review, routed evidence, or area/power recovery.
Open the run card to inspect the saved rows, methods, limits, and export files behind this step.
Inspect run card ->METHODS
Precomputed model contract.
The goal is useful study scaffolding and paper-planning discipline, not calibrated production evidence.
Original synthetic standard-cell report-literacy table based on official public OpenROAD, OpenLane, and Yosys vocabulary.
The simulation object keeps the same statement beside downloadable JSON and CSV evidence.
No Liberty table, standard-cell file, PDK, report body, command transcript, example library, or netlist is copied.
The simulation object keeps the same statement beside downloadable JSON and CSV evidence.
The browser filters saved CSV rows and exposes the model card with no-live-EDA and no-signoff boundaries.
The simulation object keeps the same statement beside downloadable JSON and CSV evidence.
LIMITS
Useful, but deliberately bounded.
No account, upload, payment, comment, newsletter, live solver, facility workflow, or product-release surface is enabled.
No live OpenROAD, OpenLane, OpenSTA, Yosys, ABC, PEX, SPICE, uploaded report parser, library ingestion, or timing closure.
Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.
No Liberty/cell-library copying, PDK redistribution, tapeout readiness, product readiness, PPA benchmark, foundry closure, or signoff claim.
Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.
Real work needs owned libraries, constraints, parasitics, tool versions, timing reports, area/power reports, and design-owner review.
Keep this boundary attached when reusing the card for lesson writing, figure planning, or research notes.
SOURCE ANCHOR
Link-only public source spine.
SemiAgora uses the source as a signal and citation anchor, then writes original summaries and original toy data with explicit limitations.
OpenROAD OpenSTA documentation
https://openroad.readthedocs.io/en/latest/main/src/sta/README.html
Open source ->