3456synthetic report rowsUNKNOWNInspect metric contract
6cell archetypesUNKNOWNInspect metric contract
0live EDA runsUNKNOWNInspect metric contract
SIMULATION / SA-EDA-STDCELL-001
Standard-cell delay, area, and pin-cap report replay
Stdcell Report Replay
A browser CSV replay for reading standard-cell drive strength, input slew, output load, pin capacitance, area, setup/hold slack, and report-stage evidence without copying libraries or running EDA tools.
EXPLORE
Start with the observable.
Use this page when the simulation is the primary artifact. The linked lesson explains the concept; the linked lab keeps the visual replay surface available.
- Filter cell archetype, drive strength, input slew, output load, report stage, and optimization goal before trusting a single slack number.
- Compare pin capacitance, load capacitance, fanout, intrinsic delay, load delay, output slew, area, leakage, setup slack, hold slack, and max-cap/max-slew risk together.
- Use the decision gate to separate setup review, hold review, max-cap/slew review, routed-evidence-needed, area/power recovery, and bounded report-reading rows.
- Keep the public boundary visible: this is not a Liberty table, copied standard-cell library, OpenROAD report, PDK collateral, timing-closure result, or signoff claim.
BROWSER INTERACTIVE LAB
Filter the saved CSV. Inspect matching replay rows.
No server solver is running here. The browser filters a precomputed table and redraws the plot locally.
Loading replay rowsReading the saved CSV in this browser.
total cell delay psoutput slew pshold slack proxy psmax cap slew riskarea pressure
Each metric is normalized independently for shape inspection. Vertical positions do not compare magnitude across metrics.
n/atotal cell delay ps
n/aoutput slew ps
n/ahold slack proxy ps
n/amax cap slew risk
n/aarea pressure
Change one or more controls to find a saved row. No unrelated CSV value is substituted.
| case id | cell label | drive strength | input slew bin | output load bin | report stage | optimization goal | pin cap ff | load cap ff | fanout ratio | total cell delay ps | output slew ps | setup slack proxy ps | hold slack proxy ps | max cap slew risk | area pressure | decision gate | next safe check |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Loading saved replay rows... | |||||||||||||||||
RUN CARD
Conditions before conclusions.
The browser filters saved CSV rows. It does not run OpenROAD, OpenLane, OpenSTA, Yosys, ABC, PEX, SPICE, uploaded report parsing, library ingestion, timing closure, or signoff.
Primary knobs
- cell archetype
- drive strength
- input slew bin
- output load bin
- report stage
- optimization goal
Saved outputs
- pin capacitance
- load capacitance
- fanout ratio
- total cell delay
- output slew
- area units
- leakage proxy
- setup slack proxy
- hold slack proxy
- max-cap/slew risk
- timing evidence score
- decision gate
EXPORT
Download the public artifacts.
These exports are the supported public files for review. PDK files and restricted third-party material are not redistributed.
Standard-cell report-literacy CSV
/data/standard-cell-delay-area-pin-cap-report-replay-v87.csv
Open file ->Typed web JSON
/data/standard-cell-delay-area-pin-cap-report-replay-web-v1.json
Open file ->Model card
/data/standard-cell-delay-area-pin-cap-report-replay-model-card-v1.md
Open file ->METHODS
How the number was made.
Methods are written for citation discipline: the extraction rule matters as much as the plotted value.
Generate a Cartesian synthetic sweep across cell archetype, drive strength, input slew bin, output load bin, report stage, and optimization goal.
Keep this method attached when reusing the figure or metric.
Compute educational proxies for pin cap, total load, fanout ratio, intrinsic delay, load delay, output slew, area, leakage, dynamic energy, setup slack, hold slack, max-cap/slew risk, and timing-evidence score.
Keep this method attached when reusing the figure or metric.
Apply decision gates that route the learner to setup timing review, hold timing review, max-cap/slew review, routed evidence, area/power recovery, or bounded report reading.
Keep this method attached when reusing the figure or metric.
Store CSV, typed JSON, model card, source links, and public boundary together with no copied Liberty, cell-library, PDK, report, or command-transcript collateral.
Keep this method attached when reusing the figure or metric.
LIMITS
What this page does not claim.
The MVP is useful because the limits are visible. These statements prevent a teaching simulation from being cited as silicon evidence.
No Liberty table, standard-cell file, LEF/DEF/GDS/SPEF/SDC, OpenROAD report body, command transcript, PDK/rule deck, or proprietary design data is copied.
Carry this boundary into any derivative note, paper draft, or slide.
No live server OpenROAD/OpenLane/OpenSTA/Yosys/ABC/PEX/SPICE execution, uploaded design/report parsing, timing closure, ECO action, or signoff workflow is active.
Carry this boundary into any derivative note, paper draft, or slide.
No tapeout readiness, product readiness, foundry closure, PPA benchmark, library ranking, or timing-closure claim is made.
Carry this boundary into any derivative note, paper draft, or slide.
Rows are normalized synthetic teaching proxies and require owned libraries, constraints, parasitics, tool versions, reports, and design-owner review before engineering reuse.
Carry this boundary into any derivative note, paper draft, or slide.
EVIDENCE
Trace the claim back to artifacts.
The evidence route remains the catalog-level browser; this page is the simulation-level reading card.
CSV replay with 3456 rows and explicit cell, drive, slew, load, stage, goal, metric, decision-gate, evidence-state, and next-check fields.
SA-EDA-STDCELL-001
Typed JSON summary with source anchors, axes, decision-gate counts, example rows, role views, and public boundary.
SA-EDA-STDCELL-001
Model card saved beside the public dataset and experiment record.
SA-EDA-STDCELL-001
Source spine uses official public OpenROAD, OpenLane, and Yosys documentation only; it does not copy tool outputs, example libraries, netlists, tables, figures, command transcripts, or proprietary collateral.
SA-EDA-STDCELL-001
Source spine
These links anchor the public teaching model. They do not convert the replay into a qualified process recipe or signoff result.
OpenROAD OpenSTA documentationOfficial source for OpenSTA, Verilog, Liberty, SDC, SPEF, SDF, VCD/SAIF, timing checks, delay calculation, and timing-report vocabulary.OpenROAD Gate Resizer documentationOfficial source for repair timing, buffer/gate sizing, max capacitance, max slew, report design area, and utilization vocabulary.OpenLane timing closure guideOfficial source for timing closure, STA, load capacitance, input slew, setup/hold, and SDC vocabulary.OpenROAD Flow Scripts tutorialOfficial tutorial source for GUI timing report, setup/hold path, path segment, slew, load, and report-navigation vocabulary.Yosys mapping to cell librariesOfficial Yosys source for ASIC cell-library mapping vocabulary without copying the example library or netlist bodies.Yosys abc command documentationOfficial Yosys command source for ABC mapping vocabulary and library-bound synthesis context.
Public execution boundary
No server-side live ngspice execution, uploads, accounts, payments, comments, newsletter signup, or job/event submissions are active on this page.