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SASemiAgoraSemiconductor knowledge & engineeringStart with dynamic Ron

DEVICE REPLAY LAB / SA-DEV-001

Replay architecture choices.
Keep PPA honest.

This lab collects the v64 advanced-device cards for FinFET fin count, GAA nanosheet electrostatics, a linked CFET contact/interconnect replay, and a GaN/SiC HEMT substrate-chain replay, and a dynamic-Ron trap-memory replay.

FinFET PPA128.1484GAA Nanosheet89.5494Stress Engineering42.523%

REPLAY CARDS

Drive, capacitance, leakage, variability, contact parasitics, GaN/SiC reliability gates, and dynamic-Ron recovery stay together.

The cards are useful because the limitation is visible: they are not calibrated TCAD or foundry data.

SA-DEV-001-FINFET-FINCOUNT-PPA-001

FinFET fin count versus PPA

Replay fin count, gate length, and Vt flavor to compare drive current, capacitance, leakage, delay index, and PPA score.

  • Add fins only after reading drive, capacitance, and leakage together.
  • Separate Vt flavor from geometry so speed and standby current do not blur.
  • Use PPA score as a bridge to ring oscillator and standard-cell consequences.
Open run card ->
SA-DEV-001-GAA-NANOSHEET-001

GAA nanosheet width, stack count, and electrostatics

Replay sheet count, nanosheet width, and variability class to compare control, drive, capacitance, Vt sigma, and PPA score.

  • Treat sheet width and stack count as coupled geometry choices.
  • Read electrostatic control, drive, capacitance, and Vt sigma together.
  • Use variability class to avoid drawing roadmap conclusions from one ideal geometry.
Open run card ->
SA-DEV-STRESS-001

Source/drain stressor strain, mobility, and deformation-risk replay

Replay architecture, channel stressor, stress proxy, and temperature to compare mobility gain, drive-current gain, Vt shift, leakage, and mechanical deformation risk.

  • Treat stress engineering as a process-to-device handoff, not only a mobility trick.
  • Compare mobility gain with Vt shift, leakage, and mechanical risk before claiming a PPA win.
  • Use FinFET, nanosheet, and CFET-watch categories to keep advanced CMOS architecture honest.
Open run card ->

Lab boundary

No live TCAD, foundry PDK, compact-model deck, process integration flow, measured-silicon claim, account, upload, payment, comment, or signoff workflow is enabled.

Open lesson packet ->