Device learning path
Concept sequence and review gate.
Open route ->DOMAIN LANE / DEVICE
Device
Device physics / TCAD / characterization
How do charge, potential, materials, thermal path, and carriers become I-V, C-V, RF, or power-device evidence?
ROUTE STACK
Start with the right surface.
This lane collects the learning packets, replay labs, simulation objects, and evidence routes that belong together. It is a filter, not a new workflow engine.
PN junction lab
Browser replay or visual evidence surface.
Open route ->MOSFET transfer lab
Browser replay or visual evidence surface.
Open route ->MOS capacitor C-V lab
Browser replay or visual evidence surface.
Open route ->Advanced device architecture lesson
Concept sequence and review gate.
Open route ->Advanced device architecture replay lab
Browser replay or visual evidence surface.
Open route ->FinFET fin count versus PPA
Typed precomputed object with methods, limits, and exports.
Open route ->GAA nanosheet width, stack count, and electrostatics
Typed precomputed object with methods, limits, and exports.
Open route ->Source/drain stressor strain, mobility, and deformation-risk replay
Typed precomputed object with methods, limits, and exports.
Open route ->CFET contact/interconnect parasitic lesson
Concept sequence and review gate.
Open route ->CFET contact/interconnect parasitic replay lab
Browser replay or visual evidence surface.
Open route ->CFET contact/interconnect parasitic map
Typed precomputed object with methods, limits, and exports.
Open route ->GaN-on-SiC HEMT substrate chain lesson
Concept sequence and review gate.
Open route ->GaN-on-SiC HEMT substrate chain replay lab
Browser replay or visual evidence surface.
Open route ->GaN-on-SiC HEMT substrate chain
Typed precomputed object with methods, limits, and exports.
Open route ->GaN dynamic-Ron and trap-memory lesson
Concept sequence and review gate.
Open route ->GaN dynamic-Ron and trap-memory replay lab
Browser replay or visual evidence surface.
Open route ->GaN dynamic-Ron and trap-memory replay
Typed precomputed object with methods, limits, and exports.
Open route ->TCAD DOE and surrogate optimization lesson
Concept sequence and review gate.
Open route ->TCAD DOE and surrogate optimization replay lab
Browser replay or visual evidence surface.
Open route ->TCAD DOE and surrogate optimization replay
Typed precomputed object with methods, limits, and exports.
Open route ->MOSFET, FinFET, GAAFET, and CFET architecture comparison lesson
Concept sequence and review gate.
Open route ->MOSFET, FinFET, GAAFET, and CFET architecture comparison lab
Browser replay or visual evidence surface.
Open route ->MOSFET, FinFET, GAAFET, and CFET architecture comparison replay
Typed precomputed object with methods, limits, and exports.
Open route ->learn/semiconductor photonics optoelectronics
Concept sequence and review gate.
Open route ->labs/semiconductor photonics optoelectronics
Browser replay or visual evidence surface.
Open route ->Semiconductor photonics causal-chain replay
Typed precomputed object with methods, limits, and exports.
Open route ->learn/rf sparameter deembedding
Concept sequence and review gate.
Open route ->labs/rf sparameter deembedding
Browser replay or visual evidence surface.
Open route ->RF S-parameter and de-embedding evidence replay
Typed precomputed object with methods, limits, and exports.
Open route ->learn/2d cfet contact parasitic ppa
Concept sequence and review gate.
Open route ->labs/2d cfet contact parasitic ppa
Browser replay or visual evidence surface.
Open route ->2D CFET contact-to-parasitic-to-PPA evidence ladder
Typed precomputed object with methods, limits, and exports.
Open route ->learn/superconducting photon detector evidence
Concept sequence and review gate.
Open route ->labs/superconducting photon detector evidence
Browser replay or visual evidence surface.
Open route ->Superconducting photon detector current-crowding and evidence map
Typed precomputed object with methods, limits, and exports.
Open route ->learn/m3d igo sram integration evidence
Concept sequence and review gate.
Open route ->labs/m3d igo sram integration evidence
Browser replay or visual evidence surface.
Open route ->Monolithic-3D Si/oxide-semiconductor SRAM integration evidence ladder
Typed precomputed object with methods, limits, and exports.
Open route ->learn/2d heterojunction ndr evidence
Concept sequence and review gate.
Open route ->labs/2d heterojunction ndr evidence
Browser replay or visual evidence surface.
Open route ->2D heterojunction NDR mechanism and evidence map
Typed precomputed object with methods, limits, and exports.
Open route ->learn/thermoelectric temperature sensor evidence
Concept sequence and review gate.
Open route ->labs/thermoelectric temperature sensor evidence
Browser replay or visual evidence surface.
Open route ->Thermoelectric temperature-sensor calibration evidence map
Typed precomputed object with methods, limits, and exports.
Open route ->learn/process device yield integration
Concept sequence and review gate.
Open route ->labs/process device yield integration
Browser replay or visual evidence surface.
Open route ->Process-device-yield integration evidence map
Typed precomputed object with methods, limits, and exports.
Open route ->SIMULATION FILTER
The existing catalog, narrowed to this domain.
Paper-writing users can enter from this page and open the relevant run cards, exports, methods, limits, and evidence without first watching a lecture.
CMOS inverter VTC and gain
Sweep VIN, plot VOUT, estimate switching point, sampled gain, and noise margins.
VM = 0.87 V|gain|max = 11.90NML 0.73 V / NMH 0.81 V
Open run card ->FinFET fin count versus PPA
Replay fin count, gate length, and Vt flavor to compare drive current, capacitance, leakage, delay index, and PPA score.
128.14841 fins / Lg 10 nm / SVT24 cases
Open run card ->GAA nanosheet width, stack count, and electrostatics
Replay sheet count, nanosheet width, and variability class to compare control, drive, capacitance, Vt sigma, and PPA score.
89.54944 sheets / 28 nm / low27 cases
Open run card ->Source/drain stressor strain, mobility, and deformation-risk replay
Replay architecture, channel stressor, stress proxy, and temperature to compare mobility gain, drive-current gain, Vt shift, leakage, and mechanical deformation risk.
42.523%64.748 cases
Open run card ->CFET contact/interconnect parasitic map
A browser CSV lab for advanced-device pathfinding: compare lateral GAA, forksheet, monolithic CFET, and sequential CFET choices against contact resistance, local interconnect capacitance, via alignment, thermal coupling, parasitic delay, energy, integration risk, and density gain before making a PPAC claim.
1728 cases4 profiles0
Open run card ->GaN-on-SiC HEMT substrate chain
A browser CSV lab for wide-bandgap device pathfinding: compare semi-insulating SiC, high-resistivity SiC, GaN-on-Si, and bonded GaN-SiC watch cases against buffer traps, RF loss, thermal path, dynamic Ron, breakdown margin, package heat path, reliability review, and application fit.
2304 cases4 profiles0
Open run card ->GaN dynamic-Ron and trap-memory replay
A browser CSV replay for reading GaN dynamic-Ron evidence as stress class, drain bias, buffer context, recovery window, temperature, current collapse, and measurement caution move together.
512050
Open run card ->TCAD DOE and surrogate optimization replay
A browser CSV replay for reading TCAD-style design-of-experiments, surrogate uncertainty, extrapolation risk, validation posture, and decision gates before treating an optimizer output as evidence.
614460
Open run card ->MOSFET, FinFET, GAAFET, and CFET architecture comparison replay
A browser CSV replay for comparing electrostatic control, footprint, contacts, capacitance, variability, thermal coupling, integration risk, evidence maturity, and circuit handoff without turning an architecture roadmap into a universal ranking.
409640
Open run card ->Semiconductor photonics causal-chain replay
A browser replay connecting photon energy, bounded LED/laser logic, ideal detector responsivity, an all-pass ring, and MZI phase transfer while exposing every missing material, solver, coupling, and measurement layer.
453650
Open run card ->RF S-parameter and de-embedding evidence replay
Compare intrinsic complex S-parameters with passive fixture embedding, four correction classes, residual-error sensitivity, stability/passivity screens, fT/fmax proxies, and a bounded noise-parameter equation.
604850
Open run card ->2D CFET contact-to-parasitic-to-PPA evidence ladder
Trace original channel and contact hypotheses through local RC, extraction and compact-model maturity, inverter/ring/logic contexts, contradiction flags, and owned replacement evidence before any PPA claim.
614440
Open run card ->Superconducting photon detector current-crowding and evidence map
Trace declared geometry and current distribution through edge/constriction pressure, illuminated or dark context, mechanism ambiguity, metrology lineage, uncertainty, contradictions, and owned replacement evidence without issuing detector design or operating guidance.
518460
Open run card ->Monolithic-3D Si/oxide-semiconductor SRAM integration evidence ladder
Trace declared device tiers and oxide-semiconductor access transport through contacts, inter-tier connectivity, WL/BL loading, thermal budget, extraction maturity, cell/subarray sensitivities, contradictions, and owned replacement evidence without copying a topology or issuing a node, architecture, or signoff claim.
614490
Open run card ->2D heterojunction NDR mechanism and evidence map
Separate rectification, consecutive negative slope, peak/valley prominence, overlap-window shape, broadening, series/contact burden, sweep history, trap-memory contradiction, mechanism ambiguity, and owned replacement evidence without fitting or reproducing a published device.
61441920
Open run card ->Thermoelectric temperature-sensor calibration evidence map
Trace normalized thermoelectric response through series-junction scaling, reference-junction correction, drift, mechanical hysteresis, cross-sensitivity, repeatability, uncertainty, contradiction review, and owned replacement-evidence gates without importing a physical calibration function or measured sensor result.
61443840
Open run card ->Process-device-yield integration evidence map
Follow bounded process variation families through device characterization, circuit margin, reliability and yield observations, three exact ledgers, four accountable role views, upstream packet postures, and a human-reviewed public-atlas gate without claiming physical causality, signoff, qualification, or production fitness.
576028800
Open run card ->DEEPENING PLAN
From concept to research artifact.
Device depth turns charge, potential, material stack, and geometry into extractable electrical curves.
Vocabulary and mechanisms
- Electrostatics ladder: junction, oxide, channel charge, depletion, inversion, and body bias.
- Transport ladder: drift, diffusion, mobility loss, saturation, leakage, and short-channel control.
- Extraction discipline: every threshold, mobility, DIBL, or capacitance number needs a condition card.
Queued seed simulations
- Threshold-voltage extraction replay comparing constant-current, gm, and linear-extrapolation views.
- Mobility and gm degradation replay that separates vertical-field and velocity-saturation effects.
- Subthreshold swing and DIBL replay with temperature, body bias, and drain-bias cards.
- Junction capacitance and breakdown vocabulary replay for depletion-width intuition.
- CFET contact/interconnect parasitic replay connecting architecture, MOL contacts, local interconnect, vias, thermal coupling, delay, energy, and PPA proxies.
- GaN-on-SiC HEMT substrate chain replay connecting substrate profile, buffer strategy, HEMT mode, thermal package path, dynamic Ron, reliability, and application fit.
- GaN dynamic-Ron and trap-memory replay connecting stress class, drain-bias class, buffer/substrate context, recovery window, temperature, current-collapse proxy, dynamic-Ron ratio, thermal risk, and next safe check.
- TCAD DOE and surrogate optimization replay connecting design levers, sampling plans, surrogate families, objective priorities, validation posture, uncertainty guards, and decision gates.
- MOSFET, FinFET, GAAFET, and CFET architecture comparison replay connecting electrostatics, footprint, contacts, capacitance, variability, heat, integration, evidence maturity, and circuit handoff.
- Semiconductor photonics causal-chain replay connecting photon energy, emitter and detector boundaries, all-pass ring response, MZI phase transfer, and replacement evidence.
- RF complex S-parameter and de-embedding replay separating intrinsic small-signal behavior, passive fixtures, correction assumptions, residual error, stability/passivity, noise, and replacement evidence.
- 2D CFET contact-to-parasitic-to-PPA evidence ladder separating transport, contact, extraction, compact-model, circuit, contradiction, and replacement-evidence states.
- SNSPD current-crowding and evidence map separating geometry, local current, edge/constriction, event context, mechanism ambiguity, metrology, uncertainty, and replacement gates.
- Oxide-semiconductor access-device and contact evidence carried into a bounded M3D SRAM cell/subarray context.
- 2D heterojunction NDR evidence map separating rectification, consecutive negative slope, peak/valley prominence, broadening, contact/series burden, sweep history, and mechanism ambiguity.
- Thermoelectric temperature-sensor evidence map separating normalized response, series-junction scaling, reference correction, drift, mechanical hysteresis, cross-sensitivity, calibration residual, uncertainty, and replacement evidence.
- Process-device-yield integration replay separating variation families, device evidence, circuit margin, reliability and yield evidence, genealogy, role review, exact ledgers, and the human-reviewed public-atlas handoff.
Claim fitness checks
- I-V and C-V condition card before any curve is reused.
- Model ladder separating analytic, compact-model, TCAD, and measured-silicon claims.
- Residual plot or extraction sensitivity note for every fitted parameter.
- CFET rows must state contact scheme, interconnect pitch, via strategy, thermal context, 3D PEX need, and no-node-ranking boundary.
- GaN/SiC rows must state substrate profile, buffer strategy, HEMT mode, thermal path, reliability context, application fit, and no-product-recommendation boundary.
- Dynamic-Ron rows must state stress window, readout/recovery window, measurement caution, and owned pulsed/switching evidence needed before any reliability claim.
- TCAD DOE rows must state mesh stability, calibration anchor, surrogate uncertainty, extrapolation risk, constraint posture, and no-solver/no-calibrated-silicon boundary.
- Architecture comparisons must state context compatibility, normalized-proxy limits, replacement evidence, device-to-circuit correlation, and no-node/no-product-ranking boundary.
- Photonics rows must separate exact constants from assumed QE, voltage, index, loss, coupling, and delta-n, then name missing material, convergence, calibration, and measurement evidence.
- RF rows must carry bias and reference-impedance definitions, fixture and correction provenance, uncertainty, broadband quality checks, compact-model lineage, and RF-owner review before a performance claim.
- A CFET PPA row must carry geometry, contact and interface metrology, bias/temperature, model and extraction provenance, circuit/layout correlation, variation, thermal context, uncertainty, and accountable review.
- An SNSPD event claim must retain detector geometry/material, current distribution, edge and defect evidence, event context, readout/timing, optical coupling, background, uncertainty, and mechanism review.
- Transport claims require owned interface, contact, bias/temperature, compact-model, variation, measurement, and circuit-handoff evidence.
- An NDR mechanism claim requires owned signed I-V sweeps, gate and temperature scope, contact/series evidence, repeatability, uncertainty, model lineage, independently reproduced transport calculations, and accountable review.
- A physical sensor claim requires owned materials, geometry, process, transfer function, reference-junction behavior, repeatability, drift, mechanical and cross-sensitivity evidence, uncertainty, traceability, and accountable review.
- Operational attribution requires owned process and equipment history, calibrated metrology, device characterization and models, circuit context, reliability and test evidence, lot-wafer-die-device genealogy, uncertainty, validation, and accountable human approval.
Paper-ready artifacts
- One extraction table with method, bias condition, and known limitation.
- One figure showing which curve region supports which claim.
- One device-to-circuit handoff note explaining what the circuit page may assume.
- One CFET tradeoff table separating density gain from contact resistance, capacitance, via alignment, delay, energy, and integration risk.
- One wide-bandgap chain table separating substrate thermal/RF evidence, buffer trap evidence, device-mode evidence, package thermal path, and reliability review.
- One GaN dynamic-Ron evidence table separating trap-memory review, recovery-window review, thermal-risk review, switching-context review, measurement-method review, and qualification-evidence-required states.
- One TCAD optimization literacy table separating mesh, calibration, uncertainty, extrapolation, constraint, owner-review, bounded-teaching, and reference-bounded states.
- One contextual architecture-comparison matrix separating electrostatic, parasitic, variability, thermal, integration, circuit-handoff, and evidence gates.
- One five-node photonics evidence matrix separating analytic relation, assumed input, source anchor, non-claim, and replacement evidence.
- One five-node RF evidence matrix separating analytic equation, assumed parameter, source anchor, non-claim, and owned-data replacement slot.
- One topic-specific four-node claim map for contact formation, compact-model extraction, CFET integration, and RC parasitic handoff.
- One six-node claim map for defects, noise, photodetection, cryogenic interfaces, instrument calibration, and traceability.
- One nine-node claim map spanning bands, DOS, alignment, transport, traps, contacts, NDR devices, electrical I-V measurement, and uncertainty.
- One seven-node claim map spanning thermal boundary, thermoelectric context, sensor transduction, repeatability/drift, calibration, uncertainty, and traceability.
Capstone Target
Build a device extraction packet that lets a circuit learner cite threshold, gm, capacitance, and leakage without overstating fidelity.
Open all-domain roadmap ->EVIDENCE BACKLOG
What this lane needs next.
The backlog keeps future additions useful rather than noisy. New pages should enter through a domain tag, public source anchor, model boundary, and precomputed evidence package.
What is already usable
- Device physics now has a bridge from PN/MOS evidence into contextual MOSFET/FinFET/GAAFET/CFET comparison, CFET contact/interconnect parasitics, GaN-on-SiC HEMT substrate chain, GaN dynamic-Ron trap-memory replay, TCAD DOE/surrogate optimization replay, and stress-engineering cards.
- Current public routes connect PN junction, MOS capacitor, MOSFET, inverter evidence, contextual MOSFET/FinFET/GAAFET/CFET comparison, FinFET PPA, GAA nanosheet electrostatics, CFET contact/interconnect parasitic replay, GaN/SiC HEMT substrate chain replay, GaN dynamic-Ron trap-memory replay, TCAD DOE/surrogate optimization replay, and source/drain stressor replay.
- Next useful additions are owned calibrated architecture-comparison compact models, Vt flavor, subthreshold swing, DIBL, measured CFET/forksheet/backside-contact replacement data, pulsed I-V dynamic Ron evidence, and calibrated TCAD DOE decks.
Good candidates
- Vt flavor selection
- subthreshold swing and DIBL
- owned pulsed I-V dynamic Ron replacement evidence
- owned architecture-comparison compact models, metrology, contact RC, and circuit correlation
- owned TCAD calibration and surrogate replacement evidence
- rights-cleared mode/FDTD convergence and calibrated optical replacement evidence
- owned bias-tagged Touchstone replacement data with calibration, de-embedding, uncertainty, and broadband quality evidence
- owned 2D CFET contact metrology, calibrated compact models, extracted-layout RC, circuit correlation, thermal/variation evidence, and accountable DTCO review
- owned SNSPD spatial current/defect evidence, detector records, optical coupling, event and timing lineage, background separation, uncertainty, and mechanism review
- owned oxide-semiconductor access-device, interface, contact, variability, compact-model, and measurement evidence for M3D SRAM handoff
- owned gate- and temperature-resolved heterojunction I-V, contact/series de-embedding, sweep-history, uncertainty, and independently reproduced transport evidence for NDR mechanism discrimination
- owned thermoelectric material/device provenance, physical transfer function, reference-junction characterization, drift, strain, cross-sensitivity, repeatability, uncertainty, and accountable review evidence
- owned process, device, circuit, reliability, test, genealogy, yield, uncertainty, and accountable review evidence for cross-domain attribution
BOUNDARIES
Useful domain content, no hidden operations.
Every domain can grow as education, simulation replay, and evidence planning. The page must not become a job board, tool controller, recipe workflow, upload service, or signoff surface.
model fidelity stated
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no measured-silicon claim without data
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no node ranking or product claim
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no substrate supplier ranking or product recommendation
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no dynamic-Ron qualification or product recommendation
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no TCAD deck, solver, optimizer, calibrated silicon, or product claim
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no architecture or node ranking, calibrated model claim, cost/yield claim, or product recommendation
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no calibrated optical performance, material model, foundry process, or photonic product claim
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no VNA control, IEEE 370 compliance, device ranking, matching recommendation, or RF signoff claim
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no A2 feasibility claim, architecture ranking, proprietary PDK/model/extraction, live solver, or PPA signoff
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no detector geometry, current, cryostat setting, fabrication recipe, calibrated performance prediction, design recommendation, product ranking, or qualification
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no oxide-semiconductor material/device ranking, calibrated transport claim, source-derived model, or production recommendation
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no source curve reuse, calibrated transport claim, mechanism proof from curve shape, material/device ranking, operating recommendation, circuit advantage, or production claim
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no copied sensor result, physical coefficient, temperature recommendation, material/device ranking, fabrication recipe, medical use, calibration service, or signoff claim
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no automatic causal attribution, equipment action, model calibration, circuit signoff, reliability qualification, product binning, wafer disposition, yield decision, or publication action
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
SOURCE SPINE
Anchors for vocabulary and scope.
These source links help name the domain. They do not convert teaching replays into certified measurements, process recipes, facility procedures, or product signoff results.
DEVSIM
Open device/TCAD candidate for future finite-volume replacement datasets.
Open source ->IEEE IRDS
Roadmap source spine for FinFET, GAA, nanosheet, forksheet, and CFET vocabulary.
Open source ->GAA nanosheet source/drain trimming study
Open paper context for GAA nanosheet parasitic RC and source/drain engineering vocabulary.
Open source ->Nanosheet deformation under stress
Open-access anchor for stress and nanosheet deformation concerns.
Open source ->Strain engineering review
Public review context for CMOS strain-engineering vocabulary.
Open source ->imec CFET logic roadmap
Public source for CFET as vertically stacked nMOS/pMOS, monolithic and sequential schemes, PPAC framing, and contact-patterning challenge vocabulary.
Open source ->imec CMOS scaling roadmap
Public source for FEOL/MOL/BEOL, contact resistance, local interconnect, via, BPR, and routing-congestion vocabulary.
Open source ->imec nanosheet to forksheet to CFET
Public source for CFET two-level local-interconnect and cell-area/routability teaching language.
Open source ->NEIGHBOR DOMAINS
Move sideways without returning home.
Semiconductor work is coupled. These links keep the site navigable when one claim crosses process, device, circuit, memory, equipment, metrology, or reliability boundaries.
Process
What changed on the wafer, and what evidence proves it?
Open domain ->Circuit
How does a device-level curve become gain, delay, and oscillation?
Open domain ->Memory
How does memory preserve, sense, move, disturb, retain, protect, and place data across SRAM, DRAM, HBM, NAND, MRAM, FeFET, SCM, CIM, and hybrid memory systems?
Open domain ->Digital / Verification
What cycle-level contract was actually checked?
Open domain ->EDA / Layout
How do layout markers, connectivity reports, parasitics, and timing evidence become a public-safe verification claim?
Open domain ->Equipment / Facilities
What tool or facility condition supports the process, and what is still not an operating instruction?
Open domain ->Metrology / Yield
Is the measurement fit for the claim?
Open domain ->Packaging / Test / Reliability
What evidence remains after the die is fabricated, bonded, packaged, screened, and stressed?
Open domain ->