CMOS inverter lesson
Concept sequence and review gate.
Open route ->DOMAIN LANE / CIRCUIT
Circuit
Analog / mixed-signal / circuit design
How does a device-level curve become gain, delay, and oscillation?
ROUTE STACK
Start with the right surface.
This lane collects the learning packets, replay labs, simulation objects, and evidence routes that belong together. It is a filter, not a new workflow engine.
CMOS inverter VTC and gain
Typed precomputed object with methods, limits, and exports.
Open route ->Ring oscillator frequency
Typed precomputed object with methods, limits, and exports.
Open route ->Analog circuit primitives lesson
Concept sequence and review gate.
Open route ->Analog primitives replay lab
Browser replay or visual evidence surface.
Open route ->Current mirror compliance and output resistance
Typed precomputed object with methods, limits, and exports.
Open route ->Sense amplifier input delta, offset, and regeneration
Typed precomputed object with methods, limits, and exports.
Open route ->Digital timing primitives lesson
Concept sequence and review gate.
Open route ->Digital timing primitives replay lab
Browser replay or visual evidence surface.
Open route ->FO4 delay and energy scaling
Typed precomputed object with methods, limits, and exports.
Open route ->learn/process device yield integration
Concept sequence and review gate.
Open route ->labs/process device yield integration
Browser replay or visual evidence surface.
Open route ->Process-device-yield integration evidence map
Typed precomputed object with methods, limits, and exports.
Open route ->SIMULATION FILTER
The existing catalog, narrowed to this domain.
Paper-writing users can enter from this page and open the relevant run cards, exports, methods, limits, and evidence without first watching a lecture.
CMOS inverter VTC and gain
Sweep VIN, plot VOUT, estimate switching point, sampled gain, and noise margins.
VM = 0.87 V|gain|max = 11.90NML 0.73 V / NMH 0.81 V
Open run card ->CMOS inverter propagation delay
Use ring-oscillator transients to extract per-stage delay across stage count and load.
td = 62.4 ps1 / 5 / 10 fF3 / 5 / 7 stages
Open run card ->Ring oscillator frequency
Close an odd inversion loop and turn inverter delay into a measurable oscillation frequency.
2.671 GHz9 oscillatorsfinal 7 periods
Open run card ->Current mirror compliance and output resistance
Replay output voltage and output resistance to see when a current mirror stops behaving like a current source.
38.17%80 kohm / 0.1 V36 cases
Open run card ->Sense amplifier input delta, offset, and regeneration
Replay input differential, offset sigma, decision probability, regeneration time, and fail-rate proxy for memory and comparator intuition.
0 ppm40 mV input / 2 mV sigma15 cases
Open run card ->FO4 delay and energy scaling
Replay VDD and temperature to connect standard-cell delay, switching energy, leakage, and an EDP-style index.
23.6891.2 V / -20 C20 cases
Open run card ->DEEPENING PLAN
From concept to research artifact.
Circuit depth links device curves to bias, gain, delay, noise, feedback, and variation.
Vocabulary and mechanisms
- Bias and operating-point literacy before AC, transient, or oscillation claims.
- Small-signal ladder: gm, gds, gain, pole, bandwidth, and loading.
- Variation ladder: corners, mismatch, Monte Carlo vocabulary, and measurement-vs-model boundary.
Queued seed simulations
- Current mirror mismatch replay with systematic ratio error and random offset cards.
- Differential pair gain and input range replay with tail-current and load sweeps.
- Comparator metastability replay linking regeneration time constant to decision margin.
- Ring oscillator PVT replay connecting inverter delay to frequency spread.
- Process-device-yield integration replay separating variation families, device evidence, circuit margin, reliability and yield evidence, genealogy, role review, exact ledgers, and the human-reviewed public-atlas handoff.
Claim fitness checks
- DC, AC, transient, and noise claims each receive a separate methods card.
- Corner and mismatch plots state whether the numbers are illustrative or PDK-derived.
- Waveform annotations point to the exact metric used by the run card.
- Operational attribution requires owned process and equipment history, calibrated metrology, device characterization and models, circuit context, reliability and test evidence, lot-wafer-die-device genealogy, uncertainty, validation, and accountable human approval.
Paper-ready artifacts
- One sizing table explaining the electrical tradeoff, not just the final width.
- One annotated waveform or Bode plot with metric definition.
- One limits note separating pre-layout and post-layout behavior.
Capstone Target
Build a compact circuit evidence packet where a device-level change propagates into gain, delay, power, or decision margin.
Open all-domain roadmap ->EVIDENCE BACKLOG
What this lane needs next.
The backlog keeps future additions useful rather than noisy. New pages should enter through a domain tag, public source anchor, model boundary, and precomputed evidence package.
What is already usable
- SA-CIR-001 has three simulation objects and a review-pending lesson packet.
- Analog primitives now add current-mirror compliance and sense-regeneration seed cards, and FO4 adds a timing bridge.
- The final video gate remains separate from the simulation evidence and the digital timing ladder.
Good candidates
- differential pair gain and input range
- comparator metastability
- standard-cell sizing
- STA path replay
- owned process, device, circuit, reliability, test, genealogy, yield, uncertainty, and accountable review evidence for cross-domain attribution
BOUNDARIES
Useful domain content, no hidden operations.
Every domain can grow as education, simulation replay, and evidence planning. The page must not become a job board, tool controller, recipe workflow, upload service, or signoff surface.
PDK condition stated
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no final video until review gate clears
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no automatic causal attribution, equipment action, model calibration, circuit signoff, reliability qualification, product binning, wafer disposition, yield decision, or publication action
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
SOURCE SPINE
Anchors for vocabulary and scope.
These source links help name the domain. They do not convert teaching replays into certified measurements, process recipes, facility procedures, or product signoff results.
Xyce
External SPICE-compatible solver reference; the public card is a precomputed educational surrogate.
Open source ->PySpice
External Python SPICE interface reference kept behind a license/dependency boundary.
Open source ->Yosys
Open synthesis source spine for future digital timing evidence packages.
Open source ->OpenROAD Flow Scripts
Open physical-design flow reference for future STA and standard-cell sizing replays.
Open source ->NEIGHBOR DOMAINS
Move sideways without returning home.
Semiconductor work is coupled. These links keep the site navigable when one claim crosses process, device, circuit, memory, equipment, metrology, or reliability boundaries.
Process
What changed on the wafer, and what evidence proves it?
Open domain ->Device
How do charge, potential, materials, thermal path, and carriers become I-V, C-V, RF, or power-device evidence?
Open domain ->Memory
How does memory preserve, sense, move, disturb, retain, protect, and place data across SRAM, DRAM, HBM, NAND, MRAM, FeFET, SCM, CIM, and hybrid memory systems?
Open domain ->Digital / Verification
What cycle-level contract was actually checked?
Open domain ->EDA / Layout
How do layout markers, connectivity reports, parasitics, and timing evidence become a public-safe verification claim?
Open domain ->Equipment / Facilities
What tool or facility condition supports the process, and what is still not an operating instruction?
Open domain ->Metrology / Yield
Is the measurement fit for the claim?
Open domain ->Packaging / Test / Reliability
What evidence remains after the die is fabricated, bonded, packaged, screened, and stressed?
Open domain ->