Physical verification lab
Browser replay or visual evidence surface.
Open route ->DOMAIN LANE / EDA / LAYOUT
EDA / Layout
Physical design / DRC / LVS / PEX / timing
How do layout markers, connectivity reports, parasitics, and timing evidence become a public-safe verification claim?
ROUTE STACK
Start with the right surface.
This lane collects the learning packets, replay labs, simulation objects, and evidence routes that belong together. It is a filter, not a new workflow engine.
Interconnect delay lab
Browser replay or visual evidence surface.
Open route ->Interconnect crosstalk lab
Browser replay or visual evidence surface.
Open route ->Power rail IR-drop lab
Browser replay or visual evidence surface.
Open route ->Physical verification evidence lesson
Concept sequence and review gate.
Open route ->Physical verification evidence replay lab
Browser replay or visual evidence surface.
Open route ->Physical verification DRC/LVS error triage
Typed precomputed object with methods, limits, and exports.
Open route ->STA Liberty path slack replay
Typed precomputed object with methods, limits, and exports.
Open route ->OpenROAD starter flow project
Supporting route.
Open route ->OpenROAD starter flow QoR parser
Typed precomputed object with methods, limits, and exports.
Open route ->SKY130 physical verification checkpoint replay
Typed precomputed object with methods, limits, and exports.
Open route ->Layout RC delay evidence lesson
Concept sequence and review gate.
Open route ->Layout RC delay replay lab
Browser replay or visual evidence surface.
Open route ->Layout RC delay evidence ladder
Typed precomputed object with methods, limits, and exports.
Open route ->Floorplan congestion, IR-drop, and clock-spine lesson
Concept sequence and review gate.
Open route ->Floorplan congestion, IR-drop, and clock-spine replay lab
Browser replay or visual evidence surface.
Open route ->Floorplan congestion, IR-drop, and clock-spine replay
Typed precomputed object with methods, limits, and exports.
Open route ->Standard-cell timing, area, and report-literacy lesson
Concept sequence and review gate.
Open route ->labs/standard cell timing area report literacy
Browser replay or visual evidence surface.
Open route ->Standard-cell delay, area, and pin-cap report replay
Typed precomputed object with methods, limits, and exports.
Open route ->CTS, routing, and IR-drop report handoff lesson
Concept sequence and review gate.
Open route ->CTS, routing, and IR-drop report handoff lab
Browser replay or visual evidence surface.
Open route ->CTS, routing, and IR-drop report handoff replay
Typed precomputed object with methods, limits, and exports.
Open route ->Open-silicon model-to-measurement evidence lesson
Concept sequence and review gate.
Open route ->Open-silicon model-to-measurement evidence lab
Browser replay or visual evidence surface.
Open route ->Open-silicon model-to-measurement evidence ladder
Typed precomputed object with methods, limits, and exports.
Open route ->SIMULATION FILTER
The existing catalog, narrowed to this domain.
Paper-writing users can enter from this page and open the relevant run cards, exports, methods, limits, and evidence without first watching a lecture.
Physical verification DRC/LVS error triage
Replay DRC and LVS issue classes as evidence cards with report confidence, triage priority, likely root cause, and safe next check.
0.975LVS / short / high18 cases
Open run card ->STA Liberty path slack replay
Replay VDD, temperature, load, and path depth to connect Liberty-style delay terms with setup slack, hold slack, and timing-report criticality.
-341.266 ps-14.47 ps81 cases
Open run card ->OpenROAD starter QoR resampling interactive lab
Filter tiny design, utilization, clock target, and buffering strategy to inspect WNS, congestion, route-risk, area, and power teaching proxies before a real reproducible flow.
144 cases4 tiny blocksQoR filter
Open run card ->OpenROAD starter flow QoR parser
Filter tiny RTL seeds, utilization, target clock, and routing effort to inspect WNS, TNS, congestion, marker-count, area, wirelength, and power proxy report fields before a real rights-cleared flow.
144 QoR cases3 tiny RTL proxies12 packages
Open run card ->SKY130 physical verification checkpoint replay
A browser CSV lab for reading DRC, LVS, PEX, and timing-handoff checkpoints as evidence, with public-safe SKY130 source anchors and no PDK collateral on the site.
192 casesDRC/LVS/PEX/timing4 proxies
Open run card ->Layout RC delay evidence ladder
A browser CSV lab that connects layout wire length, layer class, route style, load class, and checkpoint stage to RC, delay, slew, slack-risk, and evidence-state proxies.
3072 cases4 contexts4 stages
Open run card ->Floorplan congestion, IR-drop, and clock-spine replay
A browser CSV lab for physical-design report literacy: compare utilization, aspect ratio, macro channel pressure, PDN strategy, clock topology, and report stage against placement overflow, RUDY-style congestion, global-route overflow, IR-drop risk, current-density risk, skew, insertion delay, timing-slack risk, and the next safe evidence check.
4096 cases6 axes0
Open run card ->Standard-cell delay, area, and pin-cap report replay
A browser CSV replay for reading standard-cell drive strength, input slew, output load, pin capacitance, area, setup/hold slack, and report-stage evidence without copying libraries or running EDA tools.
345660
Open run card ->CTS, routing, and IR-drop report handoff replay
A browser replay that aligns clock-tree timing, route completion and RC, power-grid pressure, checkpoint maturity, owner view, and replacement evidence without running a live flow or implying signoff.
409630
Open run card ->Open-silicon model-to-measurement evidence ladder
A browser replay that separates model assumptions, cell characterization, implementation evidence, test-structure intent, measurement availability, discrepancy review, provenance, uncertainty, and claim maturity without borrowing an external project's data.
4096100
Open run card ->DEEPENING PLAN
From concept to research artifact.
EDA and layout depth converts geometry into parasitics, constraints, violations, timing, and power integrity without redistributing restricted assets.
Vocabulary and mechanisms
- Geometry ladder: device, contact, metal, via, spacing, enclosure, density, and hierarchy.
- Electrical artifact ladder: RC extraction, coupling, delay, IR drop, electromigration vocabulary, and timing model.
- Tool boundary: open examples and synthetic geometry are teaching artifacts, not signoff data.
Queued seed simulations
- Synthetic DRC and LVS mismatch gallery with cause, marker, and fix vocabulary.
- Floorplan congestion replay connecting macro placement, routing channels, and timing pressure.
- IR-drop and electromigration budget replay with current density and rail impedance proxies.
- OpenROAD/OpenLane starter flow report-parser replay connecting tiny RTL seeds, utilization, target clock, routing effort, WNS/TNS, congestion, markers, power, and SRAM peripheral proxy evidence.
- SKY130 PV checkpoint replay linking DRC markers, LVS mismatches, PEX proxies, and timing-handoff evidence.
- Layout RC delay evidence ladder showing how wire length, layer class, route style, load, and checkpoint stage move delay, slew, and slack-risk proxies.
- Floorplan congestion, IR-drop, clock-spine, and timing-risk report-literacy replay.
- Standard-cell report-literacy replay connecting drive strength, pin capacitance, load, slew, area, setup/hold slack, max-cap/max-slew risk, and evidence stage.
- CTS, routing, extracted-RC, and IR-drop report handoff replay joining independently validated PDK-free fixtures without claiming coupled flow execution.
- Open-silicon model-to-measurement evidence ladder separating assumptions, characterization, implementation, test structures, measurements, discrepancy, uncertainty, and claim maturity.
Claim fitness checks
- Every layout image states whether it is synthetic, open, or derived from an allowed tutorial.
- Every PEX or timing number states extraction assumptions and excludes signoff authority.
- Violation examples explain the rule concept without copying restricted rule decks.
- Starter-flow report parser fields are checked against sample proxy reports before any real OpenROAD/OpenLane report is accepted.
- PV checkpoint rows state source anchors, public boundaries, confidence, fix-risk proxy, and the next safe evidence check.
- Layout RC rows state estimate stage, no-SPEF/no-Liberty boundary, evidence state, and next safe report check before a timing claim.
- v84 floorplan rows keep utilization, macro blockage, PDN obstruction, CTS pressure, routing overflow, and next-safe-check evidence together.
- Standard-cell rows must state whether evidence is synthesis-only, placed estimated-RC, global-route proxy, or post-route report replay before making a timing claim.
- Cross-report rows must preserve source fixture IDs, metric contracts, hashes, checkpoint/evidence posture, owner view, readiness cap, and signoff boundary.
- External repository statements remain pinned author-claim metadata; owned replacement evidence must preserve model, report, test, measurement, condition, uncertainty, and hash lineage.
Paper-ready artifacts
- One before/after geometry card with electrical consequence.
- One parasitic table linking shape choices to delay or noise.
- One signoff-boundary note explaining what a real flow would still need.
- One repository-ready starter-flow evidence card with source spine, parser contract, sample reports, and replacement slots.
- One physical-verification checklist that separates report literacy from PDK collateral or signoff authority.
- One browser-filtered RC-to-delay table for inverter-chain, SRAM-peripheral, and counter/clock-spine teaching contexts.
- Floorplan report-literacy explainer connecting OpenROAD official vocabulary to public-safe SemiAgora CSV replay.
- One standard-cell report-literacy table separating setup review, hold review, max-cap/slew review, routed-evidence-needed, and area/power recovery states.
- One CTS/route/power-integrity handoff matrix that exposes contradictory pass flags, evidence gaps, replacement slots, and next-safe-report checks.
- One 4,096-row model-to-measurement evidence-state matrix with zero external numeric results, zero real measurement rows, explicit replacement slots, and bounded claim-maturity gates.
Capstone Target
Build a layout evidence packet that turns one geometry choice into a quantified timing, noise, or rail consequence without publishing PDK material.
Open all-domain roadmap ->EVIDENCE BACKLOG
What this lane needs next.
The backlog keeps future additions useful rather than noisy. New pages should enter through a domain tag, public source anchor, model boundary, and precomputed evidence package.
What is already usable
- Layout and EDA are intentionally public-safe: no PDK redistribution and no signoff claim.
- Existing labs teach DRC/LVS/PEX, interconnect delay, crosstalk, IR-drop, DRC/LVS triage, SKY130 PV checkpoint replay, layout RC delay replay, floorplan congestion/IR/clock-spine literacy, standard-cell timing/area literacy, CTS/routing/IR cross-report handoff, open-silicon model-to-measurement evidence, STA slack replay, and OpenROAD/OpenLane starter-flow report parsing.
- Next additions should replace v93 synthetic and empty slots with rights-cleared owned model, characterization, routed-report, test-structure, raw measurement, environment, and uncertainty evidence.
Good candidates
- floorplan congestion and IR-drop replay after layout RC
- SKY130 PV checkpoint replay with DRC/LVS/PEX/timing evidence ladder
- GitHub Actions repro-check for rights-cleared OpenROAD/OpenLane reports
- owned same-checkpoint CTS/STA, route/DRC, extracted-RC, and EM/IR replacement reports
- rights-cleared same-design model, characterization, routed-report, test-structure, and owned measurement replacement package
- reproduced ring-oscillator comparison with environment and measurement-uncertainty lineage
BOUNDARIES
Useful domain content, no hidden operations.
Every domain can grow as education, simulation replay, and evidence planning. The page must not become a job board, tool controller, recipe workflow, upload service, or signoff surface.
no PDK redistribution
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no signoff claim
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no live EDA execution, design/report upload, ECO guidance, timing/PDN signoff, or tapeout claim
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no repository mirroring, external numeric reuse, live flow, upload, signoff certification, fabrication service, measurement claim, or endorsement
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
SOURCE SPINE
Anchors for vocabulary and scope.
These source links help name the domain. They do not convert teaching replays into certified measurements, process recipes, facility procedures, or product signoff results.
Physical Verification using SKY130
Open repository signal for DRC/LVS/PEX evidence literacy; no repository code or PDK collateral is mirrored.
Open source ->OpenSTA
Open-source STA tool reference; this page does not execute OpenSTA.
Open source ->VTR OpenSTA timing tutorial
Public documentation context for timing-analysis flow vocabulary.
Open source ->VLSIDA STA tutorial
Public tutorial context for setup/hold and report-reading language.
Open source ->OpenROAD Flow Scripts tutorial
Official flow-stage vocabulary; the public page does not run OpenROAD on the server.
Open source ->OpenLane GitHub
Open-source flow path reference for a future reproducible package; no third-party code is copied into this replay.
Open source ->OpenROAD Flow Scripts GitHub
Official ORFS repository anchoring RTL-to-GDS flow-stage vocabulary and public-flow boundaries.
Open source ->OpenLane 2 documentation
Official documentation anchoring configurable open digital-ASIC flow vocabulary.
Open source ->NEIGHBOR DOMAINS
Move sideways without returning home.
Semiconductor work is coupled. These links keep the site navigable when one claim crosses process, device, circuit, memory, equipment, metrology, or reliability boundaries.
Process
What changed on the wafer, and what evidence proves it?
Open domain ->Device
How do charge, potential, materials, thermal path, and carriers become I-V, C-V, RF, or power-device evidence?
Open domain ->Circuit
How does a device-level curve become gain, delay, and oscillation?
Open domain ->Memory
How does memory preserve, sense, move, disturb, retain, protect, and place data across SRAM, DRAM, HBM, NAND, MRAM, FeFET, SCM, CIM, and hybrid memory systems?
Open domain ->Digital / Verification
What cycle-level contract was actually checked?
Open domain ->Equipment / Facilities
What tool or facility condition supports the process, and what is still not an operating instruction?
Open domain ->Metrology / Yield
Is the measurement fit for the claim?
Open domain ->Packaging / Test / Reliability
What evidence remains after the die is fabricated, bonded, packaged, screened, and stressed?
Open domain ->