Foundation
Foundation: vocabulary, mechanisms, and first-principles boundaries.
DEEPEN ALL TRACKS
Every domain gets a ladder.
Every claim keeps evidence.
A static, evidence-first plan for deepening every semiconductor domain without enabling live execution or transactional workflows.
DEPTH CONTRACT
Useful depth has four layers.
Each domain now has the same scaffold: foundation, simulation ladder, evidence ladder, and research output. That makes future additions comparable instead of scattered.
Simulation ladder
Simulation ladder: precomputed cards that expose knobs, outputs, methods, and limits.
Evidence ladder
Evidence ladder: source anchors, exports, uncertainty, and claim fitness.
Research output
Research output: paper-ready figures, tables, methods notes, and limitations.
NINE DOMAIN ROADMAPS
All domains can deepen in parallel.
The cards below are not a promise that every simulation exists today. They are the public, rights-clean backlog that keeps the platform expanding toward a comprehensive semiconductor curriculum.
Process
Process depth connects unit operation, mechanism, inline metric, device parameter, circuit timing, memory margin, and yield consequence.
- small-data virtual metrology replay
- defect pareto and inline inspection
- ALD/CVD/PVD film nonuniformity comparison
- measured replacement data for etch UQ replay
- owned APC/FDC and feedforward replacement evidence
- owned feature-profile replacement packet with physical dimensions, material provenance, profile metrology, uncertainty, and accountable process/integration review
- owned plasma-to-feature replacement packet with physical boundary distributions, material/chemistry provenance, profile metrology, uncertainty, and integration review
- SA-PROC-ETCH-ENDPOINT-011: endpoint-signal-to-profile-evidence map with independent post-process metrology, uncertainty, drift, and disposition boundaries
Device
Device depth turns charge, potential, material stack, and geometry into extractable electrical curves.
- Vt flavor selection
- subthreshold swing and DIBL
- owned pulsed I-V dynamic Ron replacement evidence
- owned calibrated TCAD DOE replacement deck with measured I-V/C-V validation
- owned architecture-comparison compact-model and extracted-RC replacement packet
- rights-cleared converged mode/FDTD and optical-measurement replacement packet
- owned rights-cleared Touchstone replacement packet with uncertainty propagation and independent broadband quality review
- owned 2D-CFET replacement packet with contact TLM/test-structure evidence, calibrated model, extracted cell, circuit correlation, and uncertainty review
- owned SNSPD replacement packet with spatial current/defect map, event/timing records, calibrated radiometry, background separation, uncertainty, and independent mechanism review
- owned 2D heterojunction NDR replacement packet with material/stack provenance, signed gate-temperature sweeps, contact de-embedding, history, uncertainty, and independently reproduced mechanism calculations
- owned thermoelectric sensor replacement packet with physical units, calibration records, reference standards, environmental/mechanical states, uncertainty, and independent review
Circuit
Circuit depth links device curves to bias, gain, delay, noise, feedback, and variation.
- differential pair gain and input range
- comparator metastability
- standard-cell sizing
- STA path replay
Memory
Memory depth now spans SRAM cell/peripheral/I/O, DRAM/HBM locality, HBM/base-die partitioning, DRAM 1T1C sensing, retention, refresh, RowHammer, ECC/scrub guardbands, NAND threshold margin, MRAM switching/read/retention, FeFET/FeRAM, PCM, ReRAM, CIM, SCM, eDRAM/MIMCAP, 3D memory, and hierarchy placement while keeping device, cell, peripheral, controller, package, system, reliability, and evidence layers separate.
- SRAM column decoder and bank I/O handoff
- compiler-style aspect ratio and words-per-row tradeoff
- measured DRAM retention, RowHammer, ECC, and scrub replacement data
- measured replacement evidence for emerging-memory placement, endurance, retention, read-margin, and integration claims
- owned M3D SRAM replacement packet with device/compact-model lineage, topology, contacts, cross-tier connectivity, thermal/process budget, layout/PEX, cell/subarray simulation, variation, measurement, uncertainty, and review
Digital / Verification
Digital depth makes cycle-level contracts, waveform evidence, assertions, timing assumptions, and fault coverage explicit.
- FSM assertion replay
- CDC synchronizer vocabulary
- BIST transition and coupling fault coverage
EDA / Layout
EDA and layout depth converts geometry into parasitics, constraints, violations, timing, and power integrity without redistributing restricted assets.
- GitHub Actions repro-check for rights-cleared OpenROAD/OpenLane reports
- rights-cleared real-tool PV report replacement package
- owned rights-cleared same-checkpoint CTS, route, extraction, and power-integrity replacement package
- rights-cleared owned model-to-silicon replacement package with ring-oscillator controls and uncertainty
Equipment / Facilities
Equipment and facilities depth teaches state, availability, environment, utilities, and EHS vocabulary while avoiding operating instructions.
- leak-rate and pumpdown vocabulary
- cleanroom recovery excursion
- OEE and RAM decomposition
- utility-load excursion
Metrology / Yield
Metrology and yield depth decides whether evidence is fit for a claim before the claim moves into process, device, or product language.
- defect pareto and wafer map
- split-lot DOE decision
- yield learning curve
- owned APC/FDC and feedforward replacement evidence
- owned raw Gauge R&R observations, analysis outputs, references, and owner review
Packaging / Test / Reliability
Packaging, test, and reliability depth follows evidence after wafer fabrication into interconnect, heat, hybrid bonding, screening, stress, and failure analysis.
- board-level parasitic and thermal interaction
- final-test guardband
- HTOL and thermal-cycle reading
- failure-analysis decision ladder
- hybrid bonding reliability evidence
BUILD SEQUENCE
Depth should accumulate, not sprawl.
For the next several passes, each new content card should land with a domain ID, a source spine, a precomputed dataset or figure, a limitation note, and a research-output target.
Capstone Target
Build a process split brief that traces one unit-process change to one measurable inline metric, one device metric, one circuit or memory consequence, and one yield evidence question.
Jump to plan ->Capstone Target
Build a device extraction packet that lets a circuit learner cite threshold, gm, capacitance, and leakage without overstating fidelity.
Jump to plan ->Capstone Target
Build a compact circuit evidence packet where a device-level change propagates into gain, delay, power, or decision margin.
Jump to plan ->Capstone Target
A memory evidence packet now travels from SRAM cell/peripheral/I/O evidence into DRAM/HBM locality, MRAM switching, RRAM/PCM/FeFET margin, CIM crossbar tradeoffs, controller traces, BIST, and ECC without blurring abstraction layers.
Jump to plan ->Capstone Target
Build a verification packet where a learner can explain exactly what behavior was checked and what remains unproven.
Jump to plan ->Capstone Target
Build a layout evidence packet that turns one geometry choice into a quantified timing, noise, or rail consequence without publishing PDK material.
Jump to plan ->Capstone Target
Build an equipment evidence packet that explains why a process result depends on environment and availability without giving operating instructions.
Jump to plan ->Capstone Target
Build a metrology packet that can approve or reject whether a graph is strong enough to support the claim attached to it.
Jump to plan ->Capstone Target
Build a post-fab evidence packet that can explain what remains uncertain after a die works electrically.
Jump to plan ->BOUNDARIES
Static education stays the product.
The roadmap deepens content and evidence. It does not add accounts, submissions, live server execution, facility-sensitive operation, or signoff authority.
Depth that is safe now
- Static curriculum planning
- Precomputed educational simulations
- Rights-clean source anchors
- Research-output checklists
- Evidence backlog prioritization
- Promoted depth seeds with precomputed datasets
Still not enabled
- No live server execution
- No accounts, uploads, payments, comments, newsletter signup, job or event submissions
- No facility operation, equipment control, recipe workflow, ATE programming, qualification signoff, or product release