Digital learning path
Concept sequence and review gate.
Open route ->DOMAIN LANE / DIGITAL / VERIFICATION
Digital / Verification
RTL / assertions / BIST / ECC
What cycle-level contract was actually checked?
ROUTE STACK
Start with the right surface.
This lane collects the learning packets, replay labs, simulation objects, and evidence routes that belong together. It is a filter, not a new workflow engine.
SRAM controller lab
Browser replay or visual evidence surface.
Open route ->SRAM BIST lab
Browser replay or visual evidence surface.
Open route ->SRAM ECC lab
Browser replay or visual evidence surface.
Open route ->Digital timing primitives lesson
Concept sequence and review gate.
Open route ->Digital timing primitives replay lab
Browser replay or visual evidence surface.
Open route ->FO4 delay and energy scaling
Typed precomputed object with methods, limits, and exports.
Open route ->STA Liberty path slack replay
Typed precomputed object with methods, limits, and exports.
Open route ->SIMULATION FILTER
The existing catalog, narrowed to this domain.
Paper-writing users can enter from this page and open the relevant run cards, exports, methods, limits, and evidence without first watching a lecture.
SRAM controller protocol trace
Replay the verified transaction trace that turns read/write requests into one-cycle checked responses.
7 / 7 checked18 cycles0 failures
Open run card ->March C- SRAM BIST fault replay
Replay 80-access March C- traces for no-fault, stuck-at-0, and stuck-at-1 SRAM scenarios.
240 total80 accesses0 / 2 / 3
Open run card ->SRAM SECDED ECC fault replay
Replay exhaustive one- and two-bit codeword fault injection for an 8-bit SECDED memory word.
92 injections13 / 13 corrected78 / 78 detected
Open run card ->FO4 delay and energy scaling
Replay VDD and temperature to connect standard-cell delay, switching energy, leakage, and an EDP-style index.
23.6891.2 V / -20 C20 cases
Open run card ->STA Liberty path slack replay
Replay VDD, temperature, load, and path depth to connect Liberty-style delay terms with setup slack, hold slack, and timing-report criticality.
-341.266 ps-14.47 ps81 cases
Open run card ->DEEPENING PLAN
From concept to research artifact.
Digital depth makes cycle-level contracts, waveform evidence, assertions, timing assumptions, and fault coverage explicit.
Vocabulary and mechanisms
- FSM vocabulary: state, transition, reset, handshake, backpressure, and latency contract.
- Waveform literacy: expected event, sampled edge, illegal sequence, and coverage point.
- Verification boundary: simulation trace, assertion, formal proof, emulation, and silicon validation are not interchangeable.
Queued seed simulations
- FSM assertion replay with passing and failing traces for one SRAM controller path.
- CDC synchronizer vocabulary replay with metastability risk and sampling-window language.
- Timing slack reading replay that separates logic delay, clock constraint, and uncertainty.
- BIST coverage replay extending stuck-at vocabulary toward transition and coupling faults.
Claim fitness checks
- Every digital claim names the contract checked and the trace or assertion supporting it.
- Coverage cards separate exercised behavior from proven absence of bugs.
- Timing examples keep STA language separate from analog waveform delay.
Paper-ready artifacts
- One waveform reading drill with expected and observed cycles.
- One assertion card with pass and fail interpretation.
- One coverage-limit note explaining what the test did not check.
Capstone Target
Build a verification packet where a learner can explain exactly what behavior was checked and what remains unproven.
Open all-domain roadmap ->EVIDENCE BACKLOG
What this lane needs next.
The backlog keeps future additions useful rather than noisy. New pages should enter through a domain tag, public source anchor, model boundary, and precomputed evidence package.
What is already usable
- Digital verification currently grows through SRAM controller, BIST, ECC evidence, FO4 timing vocabulary, and STA slack replay.
- The lane is cycle-contract and condition-card first, not arbitrary HDL compilation.
- Future pages should emphasize assertions, waveform reading, CDC vocabulary, OpenSTA reproduction packaging, and proof cards.
Good candidates
- setup/hold aperture
- CDC synchronizer MTBF
- assertion drills
BOUNDARIES
Useful domain content, no hidden operations.
Every domain can grow as education, simulation replay, and evidence planning. The page must not become a job board, tool controller, recipe workflow, upload service, or signoff surface.
no arbitrary HDL compile service
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
no user uploads
Keep this boundary attached when adding lessons, labs, simulations, resources, or research support.
SOURCE SPINE
Anchors for vocabulary and scope.
These source links help name the domain. They do not convert teaching replays into certified measurements, process recipes, facility procedures, or product signoff results.
Yosys
Open synthesis source spine for future digital timing evidence packages.
Open source ->OpenROAD Flow Scripts
Open physical-design flow reference for future STA and standard-cell sizing replays.
Open source ->Xyce
External SPICE-compatible solver reference; v64 FO4 is a precomputed surrogate.
Open source ->OpenSTA
Open-source STA tool reference; this page does not execute OpenSTA.
Open source ->VTR OpenSTA timing tutorial
Public documentation context for timing-analysis flow vocabulary.
Open source ->VLSIDA STA tutorial
Public tutorial context for setup/hold and report-reading language.
Open source ->NEIGHBOR DOMAINS
Move sideways without returning home.
Semiconductor work is coupled. These links keep the site navigable when one claim crosses process, device, circuit, memory, equipment, metrology, or reliability boundaries.
Process
What changed on the wafer, and what evidence proves it?
Open domain ->Device
How do charge, potential, materials, thermal path, and carriers become I-V, C-V, RF, or power-device evidence?
Open domain ->Circuit
How does a device-level curve become gain, delay, and oscillation?
Open domain ->Memory
How does memory preserve, sense, move, disturb, retain, protect, and place data across SRAM, DRAM, HBM, NAND, MRAM, FeFET, SCM, CIM, and hybrid memory systems?
Open domain ->EDA / Layout
How do layout markers, connectivity reports, parasitics, and timing evidence become a public-safe verification claim?
Open domain ->Equipment / Facilities
What tool or facility condition supports the process, and what is still not an operating instruction?
Open domain ->Metrology / Yield
Is the measurement fit for the claim?
Open domain ->Packaging / Test / Reliability
What evidence remains after the die is fabricated, bonded, packaged, screened, and stressed?
Open domain ->